Compare and branch instructions, with various operand widths.
Signed-off-by: Richard Henderson <[email protected]>
---
target/arm/tcg/translate-a64.c | 42 ++++++++++++++++++++++++++++++++++
target/arm/tcg/a64.decode | 9 ++++++++
2 files changed, 51 insertions(+)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 9a27c4c6ec..293aa43cc9 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -1774,6 +1774,48 @@ static bool trans_B_cond(DisasContext *s, arg_B_cond *a)
return true;
}
+static bool trans_CB_cond(DisasContext *s, arg_CB_cond *a)
+{
+ static const TCGCond cb_cond[8] = {
+ [0] = TCG_COND_GT,
+ [1] = TCG_COND_GE,
+ [2] = TCG_COND_GTU,
+ [3] = TCG_COND_GEU,
+ [4] = TCG_COND_NEVER, /* reserved */
+ [5] = TCG_COND_NEVER, /* reserved */
+ [6] = TCG_COND_EQ,
+ [7] = TCG_COND_NE,
+ };
+ TCGCond cond = cb_cond[a->cc];
+ TCGv_i64 t, m;
+
+ if (!dc_isar_feature(aa64_cmpbr, s) || cond == TCG_COND_NEVER) {
+ return false;
+ }
+
+ t = cpu_reg(s, a->rt);
+ m = cpu_reg(s, a->rm);
+ if (a->esz != MO_64) {
+ MemOp mop = a->esz | (is_signed_cond(cond) ? MO_SIGN : 0);
+ TCGv_i64 tt = tcg_temp_new_i64();
+ TCGv_i64 tm = tcg_temp_new_i64();
+
+ tcg_gen_ext_i64(tt, t, mop);
+ tcg_gen_ext_i64(tm, m, mop);
+ t = tt;
+ m = tm;
+ }
+
+ reset_btype(s);
+ DisasLabel match = gen_disas_label(s);
+
+ tcg_gen_brcond_i64(cond, t, m, match.label);
+ gen_goto_tb(s, 0, 4);
+ set_disas_label(s, match);
+ gen_goto_tb(s, 1, a->imm);
+ return true;
+}
+
static void set_btype_for_br(DisasContext *s, int rn)
{
if (dc_isar_feature(aa64_bti, s)) {
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index 01b1b3e38b..8fb1314bfc 100644
--- a/target/arm/tcg/a64.decode
+++ b/target/arm/tcg/a64.decode
@@ -208,6 +208,15 @@ TBZ . 011011 nz:1 ..... .............. rt:5
&tbz imm=%imm14 bitpos=
# B.cond and BC.cond
B_cond 0101010 0 ................... c:1 cond:4 imm=%imm19
+# CB, CBB, CBH
+%imm9 5:s9 !function=times_4
+&cb cc rt rm imm esz
+@cb . ....... cc:3 rm:5 .. ......... rt:5 &cb imm=%imm9
+CB_cond 0 1110100 ... ..... 00 ......... ..... @cb esz=2
+CB_cond 1 1110100 ... ..... 00 ......... ..... @cb esz=3
+CB_cond 0 1110100 ... ..... 10 ......... ..... @cb esz=0 # CBB
+CB_cond 0 1110100 ... ..... 11 ......... ..... @cb esz=1 # CBH
+
BR 1101011 0000 11111 000000 rn:5 00000 &r
BLR 1101011 0001 11111 000000 rn:5 00000 &r
RET 1101011 0010 11111 000000 rn:5 00000 &r
--
2.43.0
