On Fri, May 15, 2026 at 1:26 AM Conor Dooley <[email protected]> wrote: > > From: Guenter Roeck <[email protected]> > > Minimal clock register configuration required to boot Linux > without backtraces in the clock code. > > Signed-off-by: Guenter Roeck <[email protected]> > Signed-off-by: Conor Dooley <[email protected]>
Acked-by: Alistair Francis <[email protected]> Alistair > --- > I added two more cases to the switch in mchp_pfsoc_sysreg compared to > Guenter's patch, cos I still saw 2 backtraces with his patch applied. > > CC: Conor Dooley <[email protected]> > CC: Guenter Roeck <[email protected]> > CC: Alistair Francis <[email protected]> > CC: Sebastian Huber <[email protected]> > CC: [email protected] > CC: [email protected] > --- > hw/misc/mchp_pfsoc_ioscb.c | 47 +++++++++++++++++++++++++++++- > hw/misc/mchp_pfsoc_sysreg.c | 12 ++++++++ > include/hw/misc/mchp_pfsoc_ioscb.h | 2 ++ > 3 files changed, 60 insertions(+), 1 deletion(-) > > diff --git a/hw/misc/mchp_pfsoc_ioscb.c b/hw/misc/mchp_pfsoc_ioscb.c > index 05538d012a..1267d6ba4a 100644 > --- a/hw/misc/mchp_pfsoc_ioscb.c > +++ b/hw/misc/mchp_pfsoc_ioscb.c > @@ -53,6 +53,8 @@ > #define IOSCB_MAILBOX_BASE 0x07020800 > #define IOSCB_CFG_BASE 0x07080000 > #define IOSCB_CCC_BASE 0x08000000 > +#define IOSCB_PLL_NW0_BASE 0x08100000 > +#define IOSCB_PLL_NW1_BASE 0x08200000 > #define IOSCB_PLL_MSS_BASE 0x0E001000 > #define IOSCB_CFM_MSS_BASE 0x0E002000 > #define IOSCB_PLL_DDR_BASE 0x0E010000 > @@ -92,6 +94,16 @@ static const MemoryRegionOps mchp_pfsoc_dummy_ops = { > /* All PLL modules in IOSCB have the same register layout */ > > #define PLL_CTRL 0x04 > +#define PLL_REF_FB 0x08 > +#define PLL_DIV_0_1 0x10 > +#define PLL_DIV_2_3 0x14 > +#define PLL_CTRL2 0x18 > +#define PLL_CAL 0x1c > +#define PLL_PHADJ 0x20 > +#define SSCG_REG_0 0x24 > +#define SSCG_REG_1 0x28 > +#define SSCG_REG_2 0x2c > +#define SSCG_REG_3 0x30 > > static uint64_t mchp_pfsoc_pll_read(void *opaque, hwaddr offset, > unsigned size) > @@ -103,6 +115,22 @@ static uint64_t mchp_pfsoc_pll_read(void *opaque, hwaddr > offset, > /* PLL is locked */ > val = BIT(25); > break; > + case PLL_DIV_0_1: > + case PLL_DIV_2_3: > + val = 0x01000100; /* return valid post divider values */ > + break; > + case PLL_CTRL2: > + val = 0x00001110; > + break; > + case PLL_REF_FB: > + val = 0x00000100; /* RFDIV := 1 */ > + break; > + case SSCG_REG_2: > + val = 0x00000001; /* INTIN := 1 */ > + break; > + case PLL_PHADJ: > + val = 0x00000401; > + break; > default: > qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read " > "(size %d, offset 0x%" HWADDR_PRIx ")\n", > @@ -113,9 +141,18 @@ static uint64_t mchp_pfsoc_pll_read(void *opaque, hwaddr > offset, > return val; > } > > +static void mchp_pfsoc_pll_write(void *opaque, hwaddr offset, > + uint64_t value, unsigned size) > +{ > + qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write " > + "(size %d, value 0x%" PRIx64 > + ", offset 0x%" HWADDR_PRIx ")\n", > + __func__, size, value, offset); > +} > + > static const MemoryRegionOps mchp_pfsoc_pll_ops = { > .read = mchp_pfsoc_pll_read, > - .write = mchp_pfsoc_dummy_write, > + .write = mchp_pfsoc_pll_write, > .endianness = DEVICE_LITTLE_ENDIAN, > }; > > @@ -240,6 +277,14 @@ static void mchp_pfsoc_ioscb_realize(DeviceState *dev, > Error **errp) > "mchp.pfsoc.ioscb.ccc", IOSCB_CCC_REG_SIZE); > memory_region_add_subregion(&s->container, IOSCB_CCC_BASE, &s->ccc); > > + memory_region_init_io(&s->pll_nw_0, OBJECT(s), &mchp_pfsoc_pll_ops, s, > + "mchp.pfsoc.ioscb.pll_nw_0", > IOSCB_SUBMOD_REG_SIZE); > + memory_region_add_subregion(&s->container, IOSCB_PLL_NW0_BASE, > &s->pll_nw_0); > + > + memory_region_init_io(&s->pll_nw_1, OBJECT(s), &mchp_pfsoc_pll_ops, s, > + "mchp.pfsoc.ioscb.pll_nw_1", > IOSCB_SUBMOD_REG_SIZE); > + memory_region_add_subregion(&s->container, IOSCB_PLL_NW1_BASE, > &s->pll_nw_1); > + > memory_region_init_io(&s->pll_mss, OBJECT(s), &mchp_pfsoc_pll_ops, s, > "mchp.pfsoc.ioscb.pll_mss", IOSCB_SUBMOD_REG_SIZE); > memory_region_add_subregion(&s->container, IOSCB_PLL_MSS_BASE, > &s->pll_mss); > diff --git a/hw/misc/mchp_pfsoc_sysreg.c b/hw/misc/mchp_pfsoc_sysreg.c > index f190ecc78e..09389d3b1f 100644 > --- a/hw/misc/mchp_pfsoc_sysreg.c > +++ b/hw/misc/mchp_pfsoc_sysreg.c > @@ -29,6 +29,8 @@ > #include "hw/misc/mchp_pfsoc_sysreg.h" > #include "system/runstate.h" > > +#define CLOCK_CONFIG_CR 0x8 > +#define RTC_CLOCK_CR 0xc > #define MSS_RESET_CR 0x18 > #define ENVM_CR 0xb8 > #define MESSAGE_INT 0x118c > @@ -39,6 +41,16 @@ static uint64_t mchp_pfsoc_sysreg_read(void *opaque, > hwaddr offset, > uint32_t val = 0; > > switch (offset) { > + case CLOCK_CONFIG_CR: > + /* Icicle kit reference design cpu/axi/ahb divider setting */ > + val = 0x24; > + break; > + case RTC_CLOCK_CR: > + /* Bit 16 enables the RTC clock, 0x7d is the required divider > + * setting for a 125 MHz reference. > + */ > + val = BIT(16) | 0x7d; > + break; > case ENVM_CR: > /* Indicate the eNVM is running at the configured divider rate */ > val = BIT(6); > diff --git a/include/hw/misc/mchp_pfsoc_ioscb.h > b/include/hw/misc/mchp_pfsoc_ioscb.h > index eaaa2ac5d9..9687ea25b1 100644 > --- a/include/hw/misc/mchp_pfsoc_ioscb.h > +++ b/include/hw/misc/mchp_pfsoc_ioscb.h > @@ -35,6 +35,8 @@ typedef struct MchpPfSoCIoscbState { > MemoryRegion mailbox; > MemoryRegion cfg; > MemoryRegion ccc; > + MemoryRegion pll_nw_0; > + MemoryRegion pll_nw_1; > MemoryRegion pll_mss; > MemoryRegion cfm_mss; > MemoryRegion pll_ddr; > -- > 2.53.0 > >
