[PATCH v1] target/riscv: Make hpmcounterh return the upper 32-bits

[Portia Stephens]

The counter value was not being bitshifted for a hpmcounterh read
resulting in hpmcounterh returning the bottom 32-bits.
Signed-off-by: Portia Stephens <port...@tenstorrent.com>
---
 target/riscv/csr.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index cfd076b368..c522533807 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1389,8 +1389,9 @@ RISCVException riscv_pmu_read_ctr(CPURISCVState 
*env, target_ulong *val,
      */
     if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) ||
         riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) {
-        *val = riscv_pmu_ctr_get_fixed_counters_val(env, ctr_idx) -
-                                                    ctr_prev + ctr_val;
+        uint64_t cntr = riscv_pmu_ctr_get_fixed_counters_val(env, 
ctr_idx) -
+  ctr_prev + ctr_val;
+        *val = extract64(cntr, start, length);
     } else {
         *val = ctr_val;
     }
--
2.43.0