Hi, Changes from v4: https://lore.kernel.org/qemu-devel/[email protected]/ - Addressed v4 feedback and picked up Reviewed-by tags. Thanks! - Improved comments to specify optional/mandatory for CMDQ ops(patch#6) - Introduced writel_mmio for 4-byte and writell_mmio for 8-byte(patch #14) - Separated vcmdq Page0 and Page1 access helpers(patches #15, #16) - Ignore VCMDQ BASE writes if the VCMDQ is already enabled(patch #16) - Modified address_space_is_ram helper to address_space_range_is_ram() to cover the entire range(patch #18) - Allocate HW QUEUE once all pre-conditions are met(BASE write, CMDQ_ALLOC_MAP, and CMDQV / VINTF enabled) - patch #19 - Sync the VCMDQ Page0 register cache when mmap'd VINTF page0 is available(patch #20) - Introduced memory_region_skip_iommu_map()/_set_skip_iommu_map() accessors(patch 21). - Moved the renamed helper qemu_ram_backend_pagesize_min() to system/physmem.c (patch #26) - Updated commit log with DSDT/IORT AML descriptions(patch #30). - Based on top of Nathan's "Resolve AUTO properties" v3 series [0].
Please find the complete branch here: https://github.com/shamiali2008/qemu-master/tree/master-vcmdq-v5-ext Sanity tested on NVIDIA Grace. Further testing in progress. Feedback and testing are very welcome. Thanks, Shameer [0] https://lore.kernel.org/qemu-devel/[email protected]/ --- Background(from RFCv1): https://lore.kernel.org/qemu-devel/[email protected]/ Thanks to Nicolin for the initial patches and testing on which this is based. Tegra241 CMDQV extends SMMUv3 by allocating per-VM "virtual interfaces" (VINTFs), each hosting up to 128 VCMDQs. Each VINTF exposes two 64KB MMIO pages: - Page0 – guest owned control and status registers (directly mapped into the VM) - Page1 – queue configuration registers (trapped/emulated by QEMU) Unlike the standard SMMU CMDQ, a guest owned Tegra241 VCMDQ does not support the full command set. Only a subset, primarily invalidation related commands, is accepted by the CMDQV hardware. For this reason, a distinct CMDQV device must be exposed to the guest, and the guest OS must include a Tegra241 CMDQV aware driver to take advantage of the hardware acceleration. VCMDQ support is integrated via the IOMMU_HW_QUEUE_ALLOC mechanism, allowing QEMU to attach guest configured VCMDQ buffers to the underlying CMDQV hardware through IOMMUFD. The Linux kernel already supports the full CMDQV virtualisation model via IOMMUFD[0]. --- Nicolin Chen (15): backends/iommufd: Update iommufd_backend_get_device_info backends/iommufd: Update iommufd_backend_alloc_viommu to allow user ptr backends/iommufd: Introduce iommufd_backend_alloc_hw_queue backends/iommufd: Introduce iommufd_backend_viommu_mmap hw/arm/tegra241-cmdqv: Implement CMDQV init hw/arm/tegra241-cmdqv: Implement CMDQV vIOMMU alloc/free hw/arm/tegra241-cmdqv: Emulate CMDQ-V Config region hw/arm/tegra241-cmdqv: Emulate VCMDQ register reads hw/arm/tegra241-cmdqv: Emulate VCMDQ register writes hw/arm/tegra241-cmdqv: mmap VINTF Page0 for CMDQV hw/arm/tegra241-cmdqv: Allocate HW VCMDQs once configured hw/arm/tegra241-cmdqv: Map VINTF page0 into guest MMIO space hw/arm/tegra241-cmdqv: Add reset handler hw/arm/tegra241-cmdqv: Limit queue size based on backend page size hw/arm/virt-acpi: Advertise Tegra241 CMDQV nodes in DSDT Shameer Kolothum (17): system/iommufd: Remove unused viommu pointer from IOMMUFDVeventq hw/arm/smmuv3-accel: Introduce CMDQV ops interface hw/arm/tegra241-cmdqv: Add Tegra241 CMDQV ops backend stub hw/arm/smmuv3-accel: Wire CMDQV ops into accel lifecycle hw/arm/virt: Use stored SMMUv3 device list for IORT build hw/arm/tegra241-cmdqv: Probe host Tegra241 CMDQV support hw/arm/virt: Link SMMUv3 CMDQV resources to platform bus system/physmem: Add address_space_range_is_ram() helper hw/arm/tegra241-cmdqv: Use mmap'd VINTF page0 as VCMDQ backing memory: Allow RAM device regions to skip IOMMU mapping hw/arm/smmuv3-accel: Introduce common helper for veventq read hw/arm/tegra241-cmdqv: Read and propagate Tegra241 CMDQV errors system/physmem: Add qemu_ram_backend_pagesize_min() helper hw/arm/smmuv3: Add per-device identifier property hw/arm/smmuv3-accel: Introduce helper to query CMDQV type hw/arm/smmuv3-accel: Enforce viommu association when CMDQV is active hw/arm/smmuv3: Add cmdqv property for SMMUv3 device hw/arm/smmuv3-accel.h | 49 ++ hw/arm/tegra241-cmdqv.h | 381 +++++++++++++ include/hw/arm/smmuv3.h | 3 + include/hw/arm/virt.h | 1 + include/system/iommufd.h | 17 +- include/system/memory.h | 34 ++ include/system/ramblock.h | 1 + backends/iommufd.c | 64 +++ hw/arm/smmuv3-accel-stubs.c | 12 + hw/arm/smmuv3-accel.c | 196 +++++-- hw/arm/smmuv3.c | 10 + hw/arm/tegra241-cmdqv-stubs.c | 16 + hw/arm/tegra241-cmdqv.c | 1007 +++++++++++++++++++++++++++++++++ hw/arm/virt-acpi-build.c | 127 +++-- hw/arm/virt.c | 37 ++ hw/vfio/iommufd.c | 4 +- hw/vfio/listener.c | 4 + system/memory.c | 10 + system/physmem.c | 48 ++ backends/trace-events | 4 +- hw/arm/Kconfig | 5 + hw/arm/meson.build | 2 + hw/arm/trace-events | 11 + qemu-options.hx | 8 + 24 files changed, 1971 insertions(+), 80 deletions(-) create mode 100644 hw/arm/tegra241-cmdqv.h create mode 100644 hw/arm/tegra241-cmdqv-stubs.c create mode 100644 hw/arm/tegra241-cmdqv.c -- 2.43.0
