We want to allow overwriting writable fields of some ID registers. However currently some of them are never touched, neither read nor w. Examples are CLIDR_EL1, CTR_EL0, REVIDR_EL1, MIDR_EL1.
We want to initialize them from the host value, allow overwrite and write back for kvm afterwards. This patch implements the initialization. Introduce a new get_host_cpu_idregs() helper that gets the host values for all writable ID regs and store them in isar.idregs[]. Signed-off-by: Eric Auger <[email protected]> Signed-off-by: Cornelia Huck <[email protected]> --- --- target/arm/kvm.c | 72 +++++++++++++++++++++++++++++++++++++++-- target/arm/trace-events | 1 + 2 files changed, 71 insertions(+), 2 deletions(-) diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 4adfd20050..92219ee62e 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -42,6 +42,7 @@ #include "hw/acpi/ghes.h" #include "target/arm/gtimer.h" #include "migration/blocker.h" +#include "cpu-idregs.h" const KVMCapabilityInfo kvm_arch_required_capabilities[] = { KVM_CAP_INFO(DEVICE_CTRL), @@ -273,7 +274,62 @@ static uint32_t kvm_arm_sve_get_vls(int fd) return vls[0] & MAKE_64BIT_MASK(0, ARM_MAX_VQ); } -static void kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) +static int idregs_idx_to_kvm_feature_idx(ARMIDRegisterIdx idx) +{ + ARMSysRegs sysreg = id_register_sysreg[idx]; + + return KVM_ARM_FEATURE_ID_RANGE_IDX((sysreg & CP_REG_ARM64_SYSREG_OP0_MASK) + >> CP_REG_ARM64_SYSREG_OP0_SHIFT, + (sysreg & CP_REG_ARM64_SYSREG_OP1_MASK) + >> CP_REG_ARM64_SYSREG_OP1_SHIFT, + (sysreg & CP_REG_ARM64_SYSREG_CRN_MASK) + >> CP_REG_ARM64_SYSREG_CRN_SHIFT, + (sysreg & CP_REG_ARM64_SYSREG_CRM_MASK) + >> CP_REG_ARM64_SYSREG_CRM_SHIFT, + (sysreg & CP_REG_ARM64_SYSREG_OP2_MASK) + >> CP_REG_ARM64_SYSREG_OP2_SHIFT); +} + +/* + * get_host_cpu_idregs: Read all the writable ID reg host values + * + * Need to be called once the writable mask has been populated + * Note we may want to read all the known id regs but some of them are not + * writable and return an error, hence the choice of reading only those which + * are writable. Those are also readable! + */ +static int get_host_cpu_idregs(ARMCPU *cpu, int fd, ARMHostCPUFeatures *ahcf) +{ + int err = 0; + int i; + + for (i = 0; i < NUM_ID_IDX; i++) { + ARM64SysReg *sysregdesc = &arm64_id_regs[i]; + ARMSysRegs sysreg = id_register_sysreg[i]; + uint64_t writable_mask = + cpu->writable_map[idregs_idx_to_kvm_feature_idx(i)]; + uint64_t *reg; + int ret; + + if (!writable_mask) { + continue; + } + + reg = &ahcf->isar.idregs[i]; + ret = read_sys_reg64(fd, reg, idregs_sysreg_to_kvm_reg(sysreg)); + trace_get_host_cpu_idregs(sysregdesc->name, *reg); + if (ret) { + error_report("%s error reading value of host %s register (%m)", + __func__, sysregdesc->name); + + err = ret; + } + } + return err; +} + +static void +kvm_arm_get_host_cpu_features(ARMCPU *cpu, ARMHostCPUFeatures *ahcf) { /* Identify the feature bits corresponding to the host CPU, and * fill out the ARMHostCPUClass fields accordingly. To do this @@ -359,6 +415,18 @@ static void kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) SET_IDREG(&ahcf->isar, ID_AA64PFR0, 0x00000011); /* EL1&0, AArch64 only */ err = 0; } else { + /* Make sure all writable ID reg values are initialized */ + if (cpu->writable_map) { + err |= get_host_cpu_idregs(cpu, fd, ahcf); + } + + /* + * temporarily override the CLIDR_EL1 value since some host values + * trigger "Unified type is not implemented at level n" error in + * fdt_add_cpu_nodes() + */ + SET_IDREG(&ahcf->isar, CLIDR, 0x0); + err |= get_host_cpu_reg(fd, ahcf, ID_AA64PFR1_EL1_IDX); err |= get_host_cpu_reg(fd, ahcf, ID_AA64PFR2_EL1_IDX); err |= get_host_cpu_reg(fd, ahcf, ID_AA64SMFR0_EL1_IDX); @@ -485,7 +553,7 @@ void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu) CPUARMState *env = &cpu->env; if (!arm_host_cpu_features.dtb_compatible) { - kvm_arm_get_host_cpu_features(&arm_host_cpu_features); + kvm_arm_get_host_cpu_features(cpu, &arm_host_cpu_features); } cpu->kvm_target = arm_host_cpu_features.target; diff --git a/target/arm/trace-events b/target/arm/trace-events index 8502fb3265..8c7faf57c7 100644 --- a/target/arm/trace-events +++ b/target/arm/trace-events @@ -13,6 +13,7 @@ arm_gt_update_irq(int timer, int irqstate) "gt_update_irq: timer %d irqstate %d" # kvm.c kvm_arm_fixup_msi_route(uint64_t iova, uint64_t gpa) "MSI iova = 0x%"PRIx64" is translated into 0x%"PRIx64 +get_host_cpu_idregs(const char *name, uint64_t value) "scratch vcpu host value for %s is 0x%"PRIx64 # cpu.c arm_cpu_reset(uint64_t mp_aff) "cpu %" PRIu64 -- 2.53.0
