geilen takes the values 31 or 63, fix it to 8 bits. hgeie and hgeip are at most 64 bits in size, fix to 64. Update relevant function arguments and uses of hgeie and hgeip. Note, masking is widened to 64-bit as geilen is already verified to be smaller than the target long size, and an out-of-bounds shift would be UB anyway.
Signed-off-by: Anton Johansson <[email protected]> Reviewed-by: Pierrick Bouvier <[email protected]> Acked-by: Alistair Francis <[email protected]> --- target/riscv/cpu.h | 10 +++++----- target/riscv/cpu.c | 4 ++-- target/riscv/cpu_helper.c | 4 ++-- target/riscv/csr.c | 4 ++-- target/riscv/machine.c | 4 ++-- 5 files changed, 13 insertions(+), 13 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 79d3e74b7a..a2ba5bef60 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -279,7 +279,7 @@ struct CPUArchState { #ifndef CONFIG_USER_ONLY /* This contains QEMU specific information about the virt state. */ bool virt_enabled; - target_ulong geilen; + uint8_t geilen; uint64_t resetvec; uint64_t mhartid; @@ -356,8 +356,8 @@ struct CPUArchState { uint64_t htval; uint64_t htinst; uint64_t hgatp; - target_ulong hgeie; - target_ulong hgeip; + uint64_t hgeie; + uint64_t hgeip; uint64_t htimedelta; uint64_t hvien; @@ -609,8 +609,8 @@ int riscv_cpu_mirq_pending(CPURISCVState *env); int riscv_cpu_sirq_pending(CPURISCVState *env); int riscv_cpu_vsirq_pending(CPURISCVState *env); bool riscv_cpu_fp_enabled(CPURISCVState *env); -target_ulong riscv_cpu_get_geilen(CPURISCVState *env); -void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen); +uint8_t riscv_cpu_get_geilen(CPURISCVState *env); +void riscv_cpu_set_geilen(CPURISCVState *env, uint8_t geilen); bool riscv_cpu_vector_enabled(CPURISCVState *env); void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); int riscv_env_mmu_index(CPURISCVState *env, bool ifetch); diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 27310a95d1..d7219edd87 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1064,9 +1064,9 @@ static void riscv_cpu_set_irq(void *opaque, int irq, int level) } /* Update HGEIP CSR */ - env->hgeip &= ~((target_ulong)1 << irq); + env->hgeip &= ~(1ULL << irq); if (level) { - env->hgeip |= (target_ulong)1 << irq; + env->hgeip |= 1ULL << irq; } /* Update mip.SGEIP bit */ diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index ff4e941d94..e7c0ff49d0 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -712,7 +712,7 @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) } } -target_ulong riscv_cpu_get_geilen(CPURISCVState *env) +uint8_t riscv_cpu_get_geilen(CPURISCVState *env) { if (!riscv_has_ext(env, RVH)) { return 0; @@ -721,7 +721,7 @@ target_ulong riscv_cpu_get_geilen(CPURISCVState *env) return env->geilen; } -void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen) +void riscv_cpu_set_geilen(CPURISCVState *env, uint8_t geilen) { if (!riscv_has_ext(env, RVH)) { return; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index ec08fbddce..0e84554f29 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -3768,7 +3768,7 @@ static RISCVException rmw_mip64(CPURISCVState *env, int csrno, if (csrno != CSR_HVIP) { gin = get_field(env->hstatus, HSTATUS_VGEIN); - old_mip |= (env->hgeip & ((target_ulong)1 << gin)) ? MIP_VSEIP : 0; + old_mip |= (env->hgeip & (1ULL << gin)) ? MIP_VSEIP : 0; old_mip |= env->vstime_irq ? MIP_VSTIP : 0; } @@ -4953,7 +4953,7 @@ static RISCVException write_hgeie(CPURISCVState *env, int csrno, target_ulong val, uintptr_t ra) { /* Only GEILEN:1 bits implemented and BIT0 is never implemented */ - val &= ((((target_ulong)1) << env->geilen) - 1) << 1; + val &= ((1ULL << env->geilen) - 1) << 1; env->hgeie = val; /* Update mip.SGEIP bit */ riscv_cpu_update_mip(env, MIP_SGEIP, diff --git a/target/riscv/machine.c b/target/riscv/machine.c index ce5e44325d..8a8f5be8d6 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -91,8 +91,8 @@ static const VMStateDescription vmstate_hyper = { VMSTATE_UINT64(env.htval, RISCVCPU), VMSTATE_UINT64(env.htinst, RISCVCPU), VMSTATE_UINT64(env.hgatp, RISCVCPU), - VMSTATE_UINTTL(env.hgeie, RISCVCPU), - VMSTATE_UINTTL(env.hgeip, RISCVCPU), + VMSTATE_UINT64(env.hgeie, RISCVCPU), + VMSTATE_UINT64(env.hgeip, RISCVCPU), VMSTATE_UINT64(env.hvien, RISCVCPU), VMSTATE_UINT64(env.hvip, RISCVCPU), VMSTATE_UINT64(env.htimedelta, RISCVCPU), -- 2.52.0
