Hi Ericson,
On 29/4/26 23:51, Ericson Joseph wrote:
Add emulation for the Microchip PIC32MK GPK/MCM family of 32-bit MIPS
microcontrollers (DS60001519E). The family uses a MIPS32 microAptiv MCU
core running at up to 120 MHz with 256 KB SRAM and 1 MB program flash.
The following peripherals are modelled:
- EVIC — 216-source interrupt controller with SET/CLR/INV registers,
single-vector and multi-vector modes, and OFFx vector offsets
- UART — 6 instances with TX/RX FIFOs and interrupt generation;
UART1 wired to the first serial port
- Timer — 9 instances using QEMU ptimer; Timer1 drives a 1 kHz tick
- GPIO — 7 ports (A–G) with TRIS/LAT/PORT/ANSEL/CNPU/CNPD registers
- SPI — 6 instances including master and slave modes
- I2C — 4 instances (register-level stub, interrupt capable)
- DMA — 8 channels with CELL/BLOCK/PATTERN transfer modes
- CAN FD — 4 instances exposed via QEMU can-bus; SocketCAN accessible
with -object can-bus,id=canbus<n>
- USB — 2 Full-Speed OTG instances exposed as chardev PTY
- ADC — ADCHS high-speed 12-bit ADC with 7 cores and FIFO
- NVM — Flash controller with backed host-file support for persistence
- DataEE — Software data EEPROM layer over program flash
- OC — 16 Output Compare units
- IC — 16 Input Capture units
- CRU — Clock and Reset Unit (SYSCLK, PBCLK, RCON, RSWRST)
- WDT — Watchdog timer (write-once WDTKEY protocol)
- CFG — Configuration registers and SYSKEY unlock sequence
All unimplemented SFR ranges log LOG_UNIMP rather than silently ignoring
accesses. The SET (+4), CLR (+8), and INV (+C) sub-register convention
is implemented for all peripheral register banks.
The boot ROM at 0xBFC00000 contains a j 0xBFC40000 trampoline; firmware
is loaded into Boot Flash 1 at physical 0x1FC40000 via -bios.
Reference: Microchip DS60001519E (publicly available from microchip.com)
Signed-off-by: Ericson Joseph <[email protected]>
---
MAINTAINERS | 9 +
configs/targets/mipsel-softmmu.mak | 1 +
hw/mips/Kconfig | 8 +
hw/mips/meson.build | 21 +
hw/mips/pic32mk.c | 815 ++++++++++++++++++++
hw/mips/pic32mk_adchs.c | 583 ++++++++++++++
hw/mips/pic32mk_canfd.c | 1143 ++++++++++++++++++++++++++++
hw/mips/pic32mk_cfg.c | 247 ++++++
hw/mips/pic32mk_cru.c | 375 +++++++++
hw/mips/pic32mk_dataee.c | 463 +++++++++++
hw/mips/pic32mk_dma.c | 255 +++++++
hw/mips/pic32mk_evic.c | 399 ++++++++++
hw/mips/pic32mk_gpio.c | 418 ++++++++++
hw/mips/pic32mk_i2c.c | 184 +++++
hw/mips/pic32mk_ic.c | 384 ++++++++++
hw/mips/pic32mk_nvm.c | 572 ++++++++++++++
hw/mips/pic32mk_oc.c | 293 +++++++
hw/mips/pic32mk_spi.c | 532 +++++++++++++
hw/mips/pic32mk_timer.c | 294 +++++++
hw/mips/pic32mk_uart.c | 334 ++++++++
hw/mips/pic32mk_usb.c | 1033 +++++++++++++++++++++++++
hw/mips/pic32mk_wdt.c | 230 ++++++
include/hw/mips/pic32mk.h | 952 +++++++++++++++++++++++
include/hw/mips/pic32mk_adchs.h | 87 +++
include/hw/mips/pic32mk_canfd.h | 210 +++++
include/hw/mips/pic32mk_evic.h | 45 ++
include/hw/mips/pic32mk_usb.h | 181 +++++
tests/functional/mipsel/pic32mk_test_fw.S | 64 ++
tests/functional/mipsel/pic32mk_test_fw.ld | 20 +
tests/functional/mipsel/test_pic32mk.py | 92 +++
tests/qtest/pic32mk-canfd-test.c | 411 ++++++++++
tests/qtest/pic32mk-test.c | 457 +++++++++++
32 files changed, 11112 insertions(+)
This patch is HUGE, no way my human brain can review it.
Could you split it in 1 patch per hw model type? Even USB
or CAN peripherals patch will result in more than 1k LoC each.
> diff --git a/hw/mips/pic32mk_adchs.c b/hw/mips/pic32mk_adchs.c
+static void pic32mk_adchs_class_init(ObjectClass *klass, const void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ device_class_set_legacy_reset(dc, pic32mk_adchs_reset);
Also please do not use the legacy API. See for example this
commit to convert to the newer API:
https://gitlab.com/qemu-project/qemu/-/commit/ce788d3740f
Regards,
Phil.
+}
