On Sun, 17 May 2026 at 01:35, Richard Henderson
<[email protected]> wrote:
>
> Signed-off-by: Richard Henderson <[email protected]>
> ---
> target/arm/cpu-features.h | 5 +++++
> target/arm/tcg/helper-fp8-defs.h | 1 +
> target/arm/tcg/fp8_helper.c | 26 ++++++++++++++++++++++++++
> target/arm/tcg/translate-a64.c | 1 +
> target/arm/tcg/a64.decode | 1 +
> 5 files changed, 34 insertions(+)
>
> diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h
> index 8f6cc2974f..fce38dfbb0 100644
> --- a/target/arm/cpu-features.h
> +++ b/target/arm/cpu-features.h
> @@ -1625,6 +1625,11 @@ static inline bool isar_feature_aa64_f8mm8(const
> ARMISARegisters *id)
> return FIELD_EX64_IDREG(id, ID_AA64FPFR0, F8MM8);
> }
>
> +static inline bool isar_feature_aa64_f8mm4(const ARMISARegisters *id)
> +{
> + return FIELD_EX64_IDREG(id, ID_AA64FPFR0, F8MM4);
> +}
> +
> /*
> * Combinations of feature tests, for ease of use with TRANS_FEAT.
> */
> diff --git a/target/arm/tcg/helper-fp8-defs.h
> b/target/arm/tcg/helper-fp8-defs.h
> index 3c74f02022..e942308af4 100644
> --- a/target/arm/tcg/helper-fp8-defs.h
> +++ b/target/arm/tcg/helper-fp8-defs.h
> @@ -37,3 +37,4 @@ DEF_HELPER_FLAGS_5(gvec_fdot_hb, TCG_CALL_NO_RWG, void,
> ptr, ptr, ptr, env, i32)
> DEF_HELPER_FLAGS_5(gvec_fdot_idx_hb, TCG_CALL_NO_RWG, void, ptr, ptr, ptr,
> env, i32)
>
> DEF_HELPER_FLAGS_5(gvec_fmmla_sb, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env,
> i32)
> +DEF_HELPER_FLAGS_5(gvec_fmmla_hb, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env,
> i32)
> diff --git a/target/arm/tcg/fp8_helper.c b/target/arm/tcg/fp8_helper.c
> index bb1d48c3e0..d5d1fe71c5 100644
> --- a/target/arm/tcg/fp8_helper.c
> +++ b/target/arm/tcg/fp8_helper.c
> @@ -849,3 +849,29 @@ void HELPER(gvec_fmmla_sb)(void *vd, void *vn, void *vm,
> fp8_mul_finish(env, &ctx);
> clear_tail(vd, oprsz, simd_maxsz(desc));
> }
> +
> +void HELPER(gvec_fmmla_hb)(void *vd, void *vn, void *vm,
> + CPUARMState *env, uint32_t desc)
> +{
> + FP8MulContext ctx = fp8_mul_start(env, -1);
The scale_mask here should be 0xf as this is a halfprec
output, right?
> + size_t oprsz = simd_oprsz(desc);
> + size_t nseg = oprsz / 16;
> + uint32_t *n = vn;
> + uint32_t *m = vm;
> + float16 *d = vd;
> +
> + for (size_t seg = 0; seg < nseg; seg++, d += 4, n += 2, m += 2) {
> + float16 d0 = f8dotadd_h(n[0], m[0], 4, d[H4(0)], &ctx);
> + float16 d1 = f8dotadd_h(n[0], m[1], 4, d[H4(1)], &ctx);
> + float16 d2 = f8dotadd_h(n[1], m[0], 4, d[H4(2)], &ctx);
> + float16 d3 = f8dotadd_h(n[1], m[1], 4, d[H4(3)], &ctx);
> +
> + d[H4(0)] = d0;
> + d[H4(1)] = d1;
> + d[H4(2)] = d2;
> + d[H4(3)] = d3;
> + }
> +
> + fp8_mul_finish(env, &ctx);
> + clear_tail(vd, oprsz, simd_maxsz(desc));
> +}
thanks
-- PMM
