On 5/20/26 18:31, Philippe Mathieu-Daudé wrote:
Hi Kane,
On 4/2/26 11:31, Cédric Le Goater wrote:
From: Kane Chen <[email protected]>
Add an initial PWM model for Aspeed SoCs, including device state,
register definitions, and basic initialization as a sysbus device.
Signed-off-by: Cédric Le Goater <[email protected]>
Signed-off-by: Kane-Chen-AS <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
---
include/hw/arm/aspeed_soc.h | 3 +-
include/hw/misc/aspeed_pwm.h | 30 +++++++++
hw/misc/aspeed_pwm.c | 120 +++++++++++++++++++++++++++++++++++
hw/misc/meson.build | 1 +
hw/misc/trace-events | 4 ++
5 files changed, 157 insertions(+), 1 deletion(-)
create mode 100644 include/hw/misc/aspeed_pwm.h
create mode 100644 hw/misc/aspeed_pwm.c
diff --git a/hw/misc/aspeed_pwm.c b/hw/misc/aspeed_pwm.c
+static void aspeed_pwm_class_init(ObjectClass *klass, const void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->realize = aspeed_pwm_realize;
+ device_class_set_legacy_reset(dc, aspeed_pwm_reset);
Also please do not use the legacy API. See for example this
commit to convert to the newer API:
https://gitlab.com/qemu-project/qemu/-/commit/ce788d3740f
Oh ! I think this patch is from 2017 and we didn't refresh it when
it was sent :/
So, yes, Kane, if you have time for this QEMU cycle, that would be
nice.
Thanks,
C.
+ dc->desc = "Aspeed PWM Controller";
+ dc->vmsd = &vmstate_aspeed_pwm;
+}
