Signed-off-by: Richard Henderson <[email protected]>
---
target/arm/cpu-features.h | 5 +++++
target/arm/tcg/translate-sve.c | 35 ++++++++++++++++++++++++++++++++++
target/arm/tcg/sve.decode | 4 ++++
3 files changed, 44 insertions(+)
diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h
index fbce0386ef..17d6acc14d 100644
--- a/target/arm/cpu-features.h
+++ b/target/arm/cpu-features.h
@@ -1550,6 +1550,11 @@ static inline bool isar_feature_aa64_ssve_f8fma(const
ARMISARegisters *id)
return FIELD_EX64_IDREG(id, ID_AA64SMFR0, SF8FMA);
}
+static inline bool isar_feature_aa64_ssve_f8dp4(const ARMISARegisters *id)
+{
+ return FIELD_EX64_IDREG(id, ID_AA64SMFR0, SF8DP4);
+}
+
static inline bool isar_feature_aa64_sme_b16b16(const ARMISARegisters *id)
{
return FIELD_EX64_IDREG(id, ID_AA64SMFR0, B16B16);
diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c
index e23ca43f55..88e6148b83 100644
--- a/target/arm/tcg/translate-sve.c
+++ b/target/arm/tcg/translate-sve.c
@@ -8372,3 +8372,38 @@ TRANS(FMLAL_idx_hb, do_fmla_fp8, a,
gen_helper_gvec_fmla_idx_hb)
TRANS(FMLALL_sb, do_fmla_fp8, a, gen_helper_gvec_fmla_sb)
TRANS(FMLALL_idx_sb, do_fmla_fp8, a, gen_helper_gvec_fmla_idx_sb)
+
+static bool do_f8dp4(DisasContext *s, gen_helper_gvec_3_ptr *fn,
+ int rd, int rn, int rm, int index)
+{
+ bool fp8dp4 = dc_isar_feature(aa64_f8dp4, s);
+ bool ssve_fp8dp4 = dc_isar_feature(aa64_ssve_f8dp4, s);
+ bool ok = false;
+
+ /* Feature detection and enabling are complex here. */
+ if (!(ssve_fp8dp4 || (fp8dp4 && dc_isar_feature(aa64_sve2, s)))) {
+ return false;
+ }
+ if (fpmr_access_check(s)) {
+ if (fp8dp4) {
+ s->is_nonstreaming = !ssve_fp8dp4;
+ ok = sve_access_check(s);
+ } else {
+ ok = sme_sm_enabled_check(s);
+ }
+ }
+
+ if (ok) {
+ unsigned vsz = vec_full_reg_size(s);
+ tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd),
+ vec_full_reg_offset(s, rn),
+ vec_full_reg_offset(s, rm),
+ tcg_env, vsz, vsz,
+ index, fn);
+ }
+ return true;
+}
+
+TRANS(FDOT_sb, do_f8dp4, gen_helper_gvec_fdot_sb, a->rd, a->rn, a->rm, 0)
+TRANS(FDOT_idx_sb, do_f8dp4, gen_helper_gvec_fdot_idx_sb,
+ a->rd, a->rn, a->rm, a->index)
diff --git a/target/arm/tcg/sve.decode b/target/arm/tcg/sve.decode
index 06bbd7fa63..c49e992f10 100644
--- a/target/arm/tcg/sve.decode
+++ b/target/arm/tcg/sve.decode
@@ -1874,6 +1874,8 @@ FMLALL_sb 01100100 00 1 rm:5 10 idxn:2 10 rn:5
rd:5 &rxx idxm=0
FDOT_zzzz 01100100 00 1 ..... 10 0 00 0 ..... ..... @rda_rn_rm_ex esz=2
BFDOT_zzzz 01100100 01 1 ..... 10 0 00 0 ..... ..... @rda_rn_rm_ex esz=2
+FDOT_sb 01100100 01 1 ..... 10 0 00 1 ..... ..... @rda_rn_rm_ex esz=2
+
### SVE2 floating-point multiply-add long (indexed)
FMLALB_zzxw 01100100 10 1 ..... 0100.0 ..... ..... @rrxr_3a esz=2
@@ -1897,6 +1899,8 @@ FMLALL_idx_sb 01100100 idxn:2 1 .. rm:3 1100 .. rn:5
rd:5 \
FDOT_zzxz 01100100 00 1 ..... 010000 ..... ..... @rrxr_2 esz=2
BFDOT_zzxz 01100100 01 1 ..... 010000 ..... ..... @rrxr_2 esz=2
+FDOT_idx_sb 01100100 01 1 ..... 010001 ..... ..... @rrxr_2 esz=2
+
### SVE broadcast predicate element
&psel esz pd pn pm rv imm
--
2.43.0
