From: James Hilliard <[email protected]> Add the MTP0, MTP1, and MTP2 forms. MTP0 loads the low Octeon3 partial-product pair from rs/rt into P[0]/P[3], MTP1 loads the middle pair into P[1]/P[4], and MTP2 loads the high pair into P[2]/P[5]. For MTP0, also set P[1] to zero for backward compatibility with Octeon2 VMULU.
Legacy single-source encodings have rt encoded as $zero, so the same translator path also preserves the older Octeon behavior. Reviewed-by: Richard Henderson <[email protected]> Signed-off-by: James Hilliard <[email protected]> Signed-off-by: Richard Henderson <[email protected]> Signed-off-by: Philippe Mathieu-Daudé <[email protected]> Message-Id: <[email protected]> --- target/mips/tcg/octeon.decode | 4 ++++ target/mips/tcg/octeon_translate.c | 23 +++++++++++++++++++++++ 2 files changed, 27 insertions(+) diff --git a/target/mips/tcg/octeon.decode b/target/mips/tcg/octeon.decode index 5139543b153..bb0a9f1d99a 100644 --- a/target/mips/tcg/octeon.decode +++ b/target/mips/tcg/octeon.decode @@ -51,6 +51,10 @@ MTM0 011100 ..... ..... 00000 00000 001000 @r2 MTM1 011100 ..... ..... 00000 00000 001100 @r2 MTM2 011100 ..... ..... 00000 00000 001101 @r2 +MTP0 011100 ..... ..... 00000 00000 001001 @r2 +MTP1 011100 ..... ..... 00000 00000 001010 @r2 +MTP2 011100 ..... ..... 00000 00000 001011 @r2 + &saa base rt @saa ...... base:5 rt:5 ................ &saa SAA 011100 ..... ..... 00000 00000 011000 @saa diff --git a/target/mips/tcg/octeon_translate.c b/target/mips/tcg/octeon_translate.c index 26b918d649a..10c7d18ad4f 100644 --- a/target/mips/tcg/octeon_translate.c +++ b/target/mips/tcg/octeon_translate.c @@ -241,3 +241,26 @@ static bool trans_mtm(DisasContext *ctx, arg_r2 *a, unsigned int index) TRANS(MTM0, trans_mtm, 0); TRANS(MTM1, trans_mtm, 1); TRANS(MTM2, trans_mtm, 2); + +static bool trans_mtp(DisasContext *ctx, arg_r2 *a, unsigned int index) +{ + /* + * Octeon3 two-source MTP forms load lane index from rs and lane index + 3 + * from rt. Legacy one-source forms encode rt as $zero. + */ + gen_load_gpr(oct_p[index], a->rs); + gen_load_gpr(oct_p[index + 3], a->rt); + + /* + * Octeon3 clears P1 with a write to P0 so that VMULU sequences remain + * backward compatible with Octeon2. + */ + if (index == 0) { + tcg_gen_movi_i64(oct_p[1], 0); + } + return true; +} + +TRANS(MTP0, trans_mtp, 0); +TRANS(MTP1, trans_mtp, 1); +TRANS(MTP2, trans_mtp, 2); -- 2.53.0
