The RISC-V privileged specification requires SFENCE.W.INVAL and SFENCE.INVAL.IR to raise an illegal instruction exception when executed in U-mode. Check the current privilege mode during translation and reject these instructions in U-mode, so they are reported as illegal instructions.
Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3493 Signed-off-by: Zephyr Li <[email protected]> --- target/riscv/insn_trans/trans_svinval.c.inc | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/target/riscv/insn_trans/trans_svinval.c.inc b/target/riscv/insn_trans/trans_svinval.c.inc index a06c3b214f..a9bf75c7e9 100644 --- a/target/riscv/insn_trans/trans_svinval.c.inc +++ b/target/riscv/insn_trans/trans_svinval.c.inc @@ -39,6 +39,10 @@ static bool trans_sfence_w_inval(DisasContext *ctx, arg_sfence_w_inval *a) { REQUIRE_SVINVAL(ctx); REQUIRE_EXT(ctx, RVS); + + if (ctx->priv == PRV_U) { + return false; + } /* Do nothing currently */ return true; } @@ -47,6 +51,10 @@ static bool trans_sfence_inval_ir(DisasContext *ctx, arg_sfence_inval_ir *a) { REQUIRE_SVINVAL(ctx); REQUIRE_EXT(ctx, RVS); + + if (ctx->priv == PRV_U) { + return false; + } /* Do nothing currently */ return true; } -- 2.43.0
