On Wed, 20 May 2026 at 19:22, Richard Henderson <[email protected]> wrote: > > Signed-off-by: Richard Henderson <[email protected]> > --- > target/arm/cpu.h | 11 +++++++++++ > 1 file changed, 11 insertions(+) > > diff --git a/target/arm/cpu.h b/target/arm/cpu.h > index 15a13b9292..0a11dd9002 100644 > --- a/target/arm/cpu.h > +++ b/target/arm/cpu.h > @@ -1820,6 +1820,17 @@ static inline void xpsr_write(CPUARMState *env, > uint32_t val, uint32_t mask) > #define SCR_AIEN (1ULL << 46) > #define SCR_GPF (1ULL << 48) > #define SCR_MECEN (1ULL << 49) > +#define SCR_ENFPM (1ULL << 50) > +#define SCR_TMEA (1ULL << 51) > +#define SCR_TWERR (1ULL << 52) > +#define SCR_PFAREN (1ULL << 53) > +#define SCR_SRMASKEN (1ULL << 54) > +#define SCR_ENIDCP128 (1ULL << 55) > +#define SCR_DSE (1ULL << 57) > +#define SCR_ENDSE (1ULL << 58) > +#define SCR_FGTEN2 (1ULL << 59) > +#define SCR_HDBSSEN (1ULL << 60) > +#define SCR_HACEBSEN (1ULL << 61)
Typo: should be HACDBSEN. (Hardware Accelerator for Cleaning Dirty ??Bit?? State ENable. The Arm ARM doesn't say what the "B" is for but it's in the FEAT_HACDBS feature name and all the register names. "Bit" is my guess.) > #define SCR_NSE (1ULL << 62) > > /* GCSCR_ELx fields */ > -- > 2.43.0 Otherwise Reviewed-by: Peter Maydell <[email protected]> thanks -- PMM
