On Wed, 20 May 2026 at 19:28, Richard Henderson <[email protected]> wrote: > > Prepare to perform access checks for direct and > indirect uses of FPMR. > > Signed-off-by: Richard Henderson <[email protected]> > --- > target/arm/cpu.h | 1 + > target/arm/tcg/translate.h | 2 ++ > target/arm/tcg/hflags.c | 41 ++++++++++++++++++++++++++++++++++ > target/arm/tcg/translate-a64.c | 1 + > 4 files changed, 45 insertions(+) > > diff --git a/target/arm/cpu.h b/target/arm/cpu.h > index c114510446..9e637c1d80 100644 > --- a/target/arm/cpu.h > +++ b/target/arm/cpu.h > @@ -2567,6 +2567,7 @@ FIELD(TBFLAG_A64, ZT0EXC_EL, 39, 2) > FIELD(TBFLAG_A64, GCS_EN, 41, 1) > FIELD(TBFLAG_A64, GCS_RVCEN, 42, 1) > FIELD(TBFLAG_A64, GCSSTR_EL, 43, 2) > +FIELD(TBFLAG_A64, FPMR_EL, 45, 2) > > /* > * Helpers for using the above. Note that only the A64 accessors use > diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h > index 77fdc5f3a1..1648c2c96f 100644 > --- a/target/arm/tcg/translate.h > +++ b/target/arm/tcg/translate.h > @@ -199,6 +199,8 @@ typedef struct DisasContext { > uint8_t gm_blocksize; > /* True if the current insn_start has been updated. */ > bool insn_start_updated; > + /* FMPR exception EL or 0 if enabled. */
"FPMR" > +/* > + * Return the exception level to which exceptions should be taken for FPMR. > + * C.f. the ARM pseudocode function CheckFPMREnabled. This pseudocode reference is a bit misleading, because that function is for the indirect-access checks, which UNDEF to the preferred exception level, but here we're returning the EL to use for a trap on direct FPMR access. We do end up mentioning that later in fpmr_access_check(), but I think it would be useful also to say this in this comment and to also refer the reader to the access pseudocode for the FPMR register. We could also mention that this only deals with the FPMR trap bits and that generic "FP must be enabled" traps will be checked separately. Otherwise Reviewed-by: Peter Maydell <[email protected]> thanks -- PMM
