From: Portia Stephens <[email protected]>
The counter value was not being bitshifted for a hpmcounterh read
resulting in hpmcounterh returning the bottom 32-bits.
Fixes: cfc96df65e01 ("target/riscv: Remove upper_half from
riscv_pmu_ctr_get_fixed_counters_val")
Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3498
Cc: [email protected]
Signed-off-by: Portia Stephens <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
---
target/riscv/csr.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 0e4163b56b..5514e0f455 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1409,8 +1409,9 @@ RISCVException riscv_pmu_read_ctr(CPURISCVState *env,
target_ulong *val,
*/
if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) ||
riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) {
- *val = riscv_pmu_ctr_get_fixed_counters_val(env, ctr_idx) -
- ctr_prev + ctr_val;
+ uint64_t cntr = riscv_pmu_ctr_get_fixed_counters_val(env, ctr_idx) -
+ ctr_prev +
ctr_val;
+ *val = extract64(cntr, start, length);
} else {
*val = ctr_val;
}
--
2.53.0
