Add an .accessfn to the RNDR and RNDRRS system registers that traps reads to EL3 when SCR_EL3.TRNDR is set, as required by FEAT_RNG_TRAP. Mark SCR_EL3.TRNDR (bit 40) as a writable field in scr_write() when the CPU advertises the feature. The pseudocode in DDI0487 revision M.b shows the trap firing from EL0, EL1, EL2, and EL3, so there is no check of arm_current_el().
When FEAT_RNG_TRAP is implemented without FEAT_RNG, an RNDR/RNDRRS read with SCR_EL3.TRNDR=0 should UNDEF rather than succeed; handle that case in access_rndr(). Register the rndr_reginfo CP reg entries whenever either FEAT_RNG or FEAT_RNG_TRAP is implemented, so the accessfn fires even on a FEAT_RNG_TRAP-only CPU. Suggested-by: Richard Henderson <[email protected]> Signed-off-by: Jason Wright <[email protected]> --- target/arm/cpu-features.h | 5 +++++ target/arm/helper.c | 26 +++++++++++++++++++++++--- 2 files changed, 28 insertions(+), 3 deletions(-) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 4e44245a8b..a3f1406f69 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -890,6 +890,11 @@ static inline bool isar_feature_aa64_rndr(const ARMISARegisters *id) return FIELD_EX64_IDREG(id, ID_AA64ISAR0, RNDR) != 0; } +static inline bool isar_feature_aa64_rng_trap(const ARMISARegisters *id) +{ + return FIELD_EX64_IDREG(id, ID_AA64PFR1, RNDR_TRAP) != 0; +} + static inline bool isar_feature_aa64_tlbirange(const ARMISARegisters *id) { return FIELD_EX64_IDREG(id, ID_AA64ISAR0, TLB) == 2; diff --git a/target/arm/helper.c b/target/arm/helper.c index 8240f1b384..ee59dcaa26 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -787,6 +787,9 @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) if (cpu_isar_feature(aa64_mec, cpu)) { valid_mask |= SCR_MECEN; } + if (cpu_isar_feature(aa64_rng_trap, cpu)) { + valid_mask |= SCR_TRNDR; + } } else { valid_mask &= ~(SCR_RW | SCR_ST); if (cpu_isar_feature(aa32_ras, cpu)) { @@ -5294,6 +5297,22 @@ static const ARMCPRegInfo pauth_reginfo[] = { .fieldoffset = offsetof(CPUARMState, keys.apib.hi) }, }; +static CPAccessResult access_rndr(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + if (env->cp15.scr_el3 & SCR_TRNDR) { + return CP_ACCESS_TRAP_EL3; + } + /* + * Note that FEAT_RNG_TRAP may be implemented without FEAT_RNG. + * In that case, if the trap is not enabled, the read undefs. + */ + if (!cpu_isar_feature(aa64_rndr, env_archcpu(env))) { + return CP_ACCESS_UNDEFINED; + } + return CP_ACCESS_OK; +} + static uint64_t rndr_readfn(CPUARMState *env, const ARMCPRegInfo *ri) { Error *err = NULL; @@ -5325,11 +5344,11 @@ static const ARMCPRegInfo rndr_reginfo[] = { { .name = "RNDR", .state = ARM_CP_STATE_AA64, .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END | ARM_CP_IO, .opc0 = 3, .opc1 = 3, .crn = 2, .crm = 4, .opc2 = 0, - .access = PL0_R, .readfn = rndr_readfn }, + .access = PL0_R, .accessfn = access_rndr, .readfn = rndr_readfn }, { .name = "RNDRRS", .state = ARM_CP_STATE_AA64, .type = ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END | ARM_CP_IO, .opc0 = 3, .opc1 = 3, .crn = 2, .crm = 4, .opc2 = 1, - .access = PL0_R, .readfn = rndr_readfn }, + .access = PL0_R, .accessfn = access_rndr, .readfn = rndr_readfn }, }; static void dccvap_writefn(CPUARMState *env, const ARMCPRegInfo *ri, @@ -7423,7 +7442,8 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (cpu_isar_feature(aa64_pauth, cpu)) { define_arm_cp_regs(cpu, pauth_reginfo); } - if (cpu_isar_feature(aa64_rndr, cpu)) { + if (cpu_isar_feature(aa64_rndr, cpu) || + cpu_isar_feature(aa64_rng_trap, cpu)) { define_arm_cp_regs(cpu, rndr_reginfo); } /* Data Cache clean instructions up to PoP */ -- 2.50.1 (Apple Git-155)
