On Fri, May 15, 2026 at 5:47 AM Daniel Henrique Barboza <[email protected]> wrote: > > The priv spec states the following about mstatus.MPV: > > "The MPV bit (Machine Previous Virtualization Mode) is written by the > implementation whenever a trap is taken into M-mode." > > And, about mstatus.GVA: > > "Field GVA (Guest Virtual Address) is written by the implementation > whenever a trap is taken into M-mode." > > Both are written during riscv_cpu_do_interrupt(). They're not supposed > to be written by userspace. As far as write_mstatus goes these fields > are read only. The same applies for mstatush.MPV/mstatush.GVA. > > Fixes: 03dd405dd5 ("target/riscv: Support MSTATUS.MPV/GVA only when RVH is > enabled") > Signed-off-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Alistair Francis <[email protected]> Alistair > --- > target/riscv/csr.c | 5 +---- > 1 file changed, 1 insertion(+), 4 deletions(-) > > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index e1cd4a299c..74f5f868f0 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -2040,9 +2040,6 @@ static RISCVException write_mstatus(CPURISCVState *env, > int csrno, > } > > if (xl != MXL_RV32 || env->debugger) { > - if (riscv_has_ext(env, RVH)) { > - mask |= MSTATUS_MPV | MSTATUS_GVA; > - } > if ((val & MSTATUS64_UXL) != 0) { > mask |= MSTATUS64_UXL; > } > @@ -2079,7 +2076,7 @@ static RISCVException write_mstatush(CPURISCVState > *env, int csrno, > target_ulong val, uintptr_t ra) > { > uint64_t valh = (uint64_t)val << 32; > - uint64_t mask = riscv_has_ext(env, RVH) ? MSTATUS_MPV | MSTATUS_GVA : 0; > + uint64_t mask = 0; > > if (riscv_cpu_cfg(env)->ext_smdbltrp) { > mask |= MSTATUS_MDT; > -- > 2.43.0 > >
