New structure CPUSysState is added here, it contains CSR registers now, in future TLB and timer can be moved to this structure also.
It is only code movement, no function change. Signed-off-by: Bibo Mao <[email protected]> --- target/loongarch/cpu.c | 4 +- target/loongarch/cpu.h | 35 +++++------ target/loongarch/csr.c | 4 +- target/loongarch/csr.h | 2 +- target/loongarch/machine.c | 116 ++++++++++++++++++------------------- 5 files changed, 81 insertions(+), 80 deletions(-) diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index a036355e0c..f918fd94b8 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -282,7 +282,7 @@ static void loongarch_la464_initfn(Object *obj) uint32_t data = 0, field; int i; - set_current_state(env, env); + set_current_state(env, &env->sys_env[0]); for (i = 0; i < 21; i++) { env->cpucfg[i] = 0x0; } @@ -412,7 +412,7 @@ static void loongarch_la132_initfn(Object *obj) uint32_t data = 0; int i; - set_current_state(env, env); + set_current_state(env, &env->sys_env[0]); for (i = 0; i < 21; i++) { env->cpucfg[i] = 0x0; } diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index dedb3971e5..9787ad2ec6 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -317,23 +317,7 @@ typedef struct LoongArchBT { #define CPU_VENDOR_LOONGSON "Loongson" #define CPU_MODEL_3A5000 "3A5000" #define CPU_MODEL_1C101 "1C101" -struct CPUArchState; -typedef struct CPUArchState CPUSysState; - -typedef struct CPUArchState { - uint64_t gpr[32]; - uint64_t pc; - - fpr_t fpr[32]; - bool cf[8]; - uint32_t fcsr0; - lbt_t lbt; - - uint32_t cpucfg[21]; - uint32_t pv_features; - uint64_t vendor_id; - uint64_t cpu_id; - +typedef struct CPUSysState { /* LoongArch CSRs */ uint64_t CSR_CRMD; uint64_t CSR_PRMD; @@ -395,6 +379,23 @@ typedef struct CPUArchState { uint64_t CSR_MSGIS[N_MSGIS]; uint64_t CSR_MSGIR; uint64_t CSR_MSGIE; +} CPUSysState; + +typedef struct CPUArchState { + uint64_t gpr[32]; + uint64_t pc; + + fpr_t fpr[32]; + bool cf[8]; + uint32_t fcsr0; + lbt_t lbt; + + uint32_t cpucfg[21]; + uint32_t pv_features; + uint64_t vendor_id; + uint64_t cpu_id; + CPUSysState sys_env[1]; + struct { uint64_t guest_addr; } stealtime; diff --git a/target/loongarch/csr.c b/target/loongarch/csr.c index d759be316b..9678948c45 100644 --- a/target/loongarch/csr.c +++ b/target/loongarch/csr.c @@ -9,14 +9,14 @@ #define CSR_OFF_FUNCS(NAME, FL, RD, WR) \ [LOONGARCH_CSR_##NAME] = { \ .name = (stringify(NAME)), \ - .offset = offsetof(CPULoongArchState, CSR_##NAME), \ + .offset = offsetof(CPUSysState, CSR_##NAME), \ .flags = FL, .readfn = RD, .writefn = WR \ } #define CSR_OFF_ARRAY(NAME, N) \ [LOONGARCH_CSR_##NAME(N)] = { \ .name = (stringify(NAME##N)), \ - .offset = offsetof(CPULoongArchState, CSR_##NAME[N]), \ + .offset = offsetof(CPUSysState, CSR_##NAME[N]), \ .flags = CSRFL_BASIC, .readfn = NULL, .writefn = NULL \ } diff --git a/target/loongarch/csr.h b/target/loongarch/csr.h index ed7c603a0b..6841968b80 100644 --- a/target/loongarch/csr.h +++ b/target/loongarch/csr.h @@ -29,6 +29,6 @@ CSRInfo *get_csr(unsigned int csr_num); bool set_csr_flag(unsigned int csr_num, int flag); static inline int get_csr_offset(const CSRInfo *csr, int vm_level) { - return csr->offset; + return csr->offset + offsetof(CPULoongArchState, sys_env[vm_level]); } #endif /* TARGET_LOONGARCH_CSR_H */ diff --git a/target/loongarch/machine.c b/target/loongarch/machine.c index 4db53fec26..a54c5d18a4 100644 --- a/target/loongarch/machine.c +++ b/target/loongarch/machine.c @@ -58,9 +58,9 @@ static const VMStateDescription vmstate_msgint = { .minimum_version_id = 1, .needed = msgint_needed, .fields = (const VMStateField[]) { - VMSTATE_UINT64_ARRAY(env.CSR_MSGIS, LoongArchCPU, N_MSGIS), - VMSTATE_UINT64(env.CSR_MSGIR, LoongArchCPU), - VMSTATE_UINT64(env.CSR_MSGIE, LoongArchCPU), + VMSTATE_UINT64_ARRAY(env.sys_env[0].CSR_MSGIS, LoongArchCPU, N_MSGIS), + VMSTATE_UINT64(env.sys_env[0].CSR_MSGIR, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_MSGIE, LoongArchCPU), VMSTATE_END_OF_LIST() }, }; @@ -167,8 +167,8 @@ static const VMStateDescription vmstate_pmu = { .needed = pmu_needed, .fields = (const VMStateField[]) { VMSTATE_UINT32(env.perf_event_num, LoongArchCPU), - VMSTATE_UINT64_ARRAY(env.CSR_PERFCTRL, LoongArchCPU, MAX_PERF_EVENTS), - VMSTATE_UINT64_ARRAY(env.CSR_PERFCNTR, LoongArchCPU, MAX_PERF_EVENTS), + VMSTATE_UINT64_ARRAY(env.sys_env[0].CSR_PERFCTRL, LoongArchCPU, MAX_PERF_EVENTS), + VMSTATE_UINT64_ARRAY(env.sys_env[0].CSR_PERFCNTR, LoongArchCPU, MAX_PERF_EVENTS), VMSTATE_END_OF_LIST() }, }; @@ -215,61 +215,61 @@ const VMStateDescription vmstate_loongarch_cpu = { VMSTATE_UINT64(env.pc, LoongArchCPU), /* Remaining CSRs */ - VMSTATE_UINT64(env.CSR_CRMD, LoongArchCPU), - VMSTATE_UINT64(env.CSR_PRMD, LoongArchCPU), - VMSTATE_UINT64(env.CSR_EUEN, LoongArchCPU), - VMSTATE_UINT64(env.CSR_MISC, LoongArchCPU), - VMSTATE_UINT64(env.CSR_ECFG, LoongArchCPU), - VMSTATE_UINT64(env.CSR_ESTAT, LoongArchCPU), - VMSTATE_UINT64(env.CSR_ERA, LoongArchCPU), - VMSTATE_UINT64(env.CSR_BADV, LoongArchCPU), - VMSTATE_UINT64(env.CSR_BADI, LoongArchCPU), - VMSTATE_UINT64(env.CSR_EENTRY, LoongArchCPU), - VMSTATE_UINT64(env.CSR_TLBIDX, LoongArchCPU), - VMSTATE_UINT64(env.CSR_TLBEHI, LoongArchCPU), - VMSTATE_UINT64(env.CSR_TLBELO0, LoongArchCPU), - VMSTATE_UINT64(env.CSR_TLBELO1, LoongArchCPU), - VMSTATE_UINT64(env.CSR_ASID, LoongArchCPU), - VMSTATE_UINT64(env.CSR_PGDL, LoongArchCPU), - VMSTATE_UINT64(env.CSR_PGDH, LoongArchCPU), - VMSTATE_UINT64(env.CSR_PGD, LoongArchCPU), - VMSTATE_UINT64(env.CSR_PWCL, LoongArchCPU), - VMSTATE_UINT64(env.CSR_PWCH, LoongArchCPU), - VMSTATE_UINT64(env.CSR_STLBPS, LoongArchCPU), - VMSTATE_UINT64(env.CSR_RVACFG, LoongArchCPU), - VMSTATE_UINT64(env.CSR_PRCFG1, LoongArchCPU), - VMSTATE_UINT64(env.CSR_PRCFG2, LoongArchCPU), - VMSTATE_UINT64(env.CSR_PRCFG3, LoongArchCPU), - VMSTATE_UINT64_ARRAY(env.CSR_SAVE, LoongArchCPU, 16), - VMSTATE_UINT64(env.CSR_TID, LoongArchCPU), - VMSTATE_UINT64(env.CSR_TCFG, LoongArchCPU), - VMSTATE_UINT64(env.CSR_TVAL, LoongArchCPU), - VMSTATE_UINT64(env.CSR_CNTC, LoongArchCPU), - VMSTATE_UINT64(env.CSR_TICLR, LoongArchCPU), - VMSTATE_UINT64(env.CSR_LLBCTL, LoongArchCPU), - VMSTATE_UINT64(env.CSR_IMPCTL1, LoongArchCPU), - VMSTATE_UINT64(env.CSR_IMPCTL2, LoongArchCPU), - VMSTATE_UINT64(env.CSR_TLBRENTRY, LoongArchCPU), - VMSTATE_UINT64(env.CSR_TLBRBADV, LoongArchCPU), - VMSTATE_UINT64(env.CSR_TLBRERA, LoongArchCPU), - VMSTATE_UINT64(env.CSR_TLBRSAVE, LoongArchCPU), - VMSTATE_UINT64(env.CSR_TLBRELO0, LoongArchCPU), - VMSTATE_UINT64(env.CSR_TLBRELO1, LoongArchCPU), - VMSTATE_UINT64(env.CSR_TLBREHI, LoongArchCPU), - VMSTATE_UINT64(env.CSR_TLBRPRMD, LoongArchCPU), - VMSTATE_UINT64(env.CSR_MERRCTL, LoongArchCPU), - VMSTATE_UINT64(env.CSR_MERRINFO1, LoongArchCPU), - VMSTATE_UINT64(env.CSR_MERRINFO2, LoongArchCPU), - VMSTATE_UINT64(env.CSR_MERRENTRY, LoongArchCPU), - VMSTATE_UINT64(env.CSR_MERRERA, LoongArchCPU), - VMSTATE_UINT64(env.CSR_MERRSAVE, LoongArchCPU), - VMSTATE_UINT64(env.CSR_CTAG, LoongArchCPU), - VMSTATE_UINT64_ARRAY(env.CSR_DMW, LoongArchCPU, 4), + VMSTATE_UINT64(env.sys_env[0].CSR_CRMD, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_PRMD, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_EUEN, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_MISC, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_ECFG, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_ESTAT, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_ERA, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_BADV, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_BADI, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_EENTRY, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_TLBIDX, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_TLBEHI, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_TLBELO0, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_TLBELO1, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_ASID, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_PGDL, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_PGDH, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_PGD, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_PWCL, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_PWCH, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_STLBPS, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_RVACFG, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_PRCFG1, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_PRCFG2, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_PRCFG3, LoongArchCPU), + VMSTATE_UINT64_ARRAY(env.sys_env[0].CSR_SAVE, LoongArchCPU, 16), + VMSTATE_UINT64(env.sys_env[0].CSR_TID, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_TCFG, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_TVAL, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_CNTC, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_TICLR, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_LLBCTL, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_IMPCTL1, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_IMPCTL2, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_TLBRENTRY, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_TLBRBADV, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_TLBRERA, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_TLBRSAVE, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_TLBRELO0, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_TLBRELO1, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_TLBREHI, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_TLBRPRMD, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_MERRCTL, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_MERRINFO1, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_MERRINFO2, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_MERRENTRY, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_MERRERA, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_MERRSAVE, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_CTAG, LoongArchCPU), + VMSTATE_UINT64_ARRAY(env.sys_env[0].CSR_DMW, LoongArchCPU, 4), /* Debug CSRs */ - VMSTATE_UINT64(env.CSR_DBG, LoongArchCPU), - VMSTATE_UINT64(env.CSR_DERA, LoongArchCPU), - VMSTATE_UINT64(env.CSR_DSAVE, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_DBG, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_DERA, LoongArchCPU), + VMSTATE_UINT64(env.sys_env[0].CSR_DSAVE, LoongArchCPU), VMSTATE_UINT64(kvm_state_counter, LoongArchCPU), /* PV steal time */ -- 2.39.3
