Re: [PULL 37/48] target/riscv: do not set defaults in cpu prop callback

[Philippe Mathieu-Daudé]

On 22/5/26 02:03, alistai...@gmail.com wrote:

From: Daniel Henrique Barboza <daniel.barb...@oss.qualcomm.com>

Do not rely on riscv_cpu_* arrays to set rv32/rv64 CPU defaults - add
them to the CPU definition like we do with all other CPUs (aside from
'max').

Hmm this change is unfortunate, I was about to replace the 3 machine
uses of TYPE_RISCV_CPU_BASE by "max" (they were semantically identical).

Why do we need these "base" CPU types and can't use "max" instead?
Because they are "fake but stable" why "max" doesn't aim to be?

Signed-off-by: Daniel Henrique Barboza <daniel.barb...@oss.qualcomm.com>
Acked-by: Alistair Francis <alistair.fran...@wdc.com>
Message-ID: <20260512032926.1978818-13-daniel.barb...@oss.qualcomm.com>
Signed-off-by: Alistair Francis <alistair.fran...@wdc.com>
---
  target/riscv/cpu.c         | 40 ++++++++++++++++++++++++++++++++++++++
  target/riscv/tcg/tcg-cpu.c | 14 -------------
  2 files changed, 40 insertions(+), 14 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 64e3fa4ef0..5d3383f335 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -3076,6 +3076,26 @@ static const TypeInfo riscv_cpu_type_infos[] = {
      DEFINE_RISCV_CPU(TYPE_RISCV_CPU_BASE32, TYPE_RISCV_DYNAMIC_CPU,
          .cfg.max_satp_mode = VM_1_10_SV32,
          .misa_mxl_max = MXL_RV32,
+
+        /*  Default extensions as of QEMU 11.1.  */
+        .cfg.ext_zicbom = true,
+        .cfg.ext_zicbop = true,
+        .cfg.ext_zicboz = true,
+        .cfg.ext_zicntr = true,
+        .cfg.ext_zicsr = true,
+        .cfg.ext_zifencei = true,
+        .cfg.ext_zihintntl = true,
+        .cfg.ext_zihintpause = true,
+        .cfg.ext_zihpm = true,
+        .cfg.ext_zawrs = true,
+        .cfg.ext_zfa = true,
+        .cfg.ext_zba = true,
+        .cfg.ext_zbb = true,
+        .cfg.ext_zbc = true,
+        .cfg.ext_zbs = true,
+        .cfg.ext_sstc = true,
+        .cfg.ext_svadu = true,
+        .cfg.ext_svvptc = true,
      ),

DEFINE_RISCV_CPU(TYPE_RISCV_CPU_IBEX, TYPE_RISCV_VENDOR_CPU,

@@ -3128,6 +3148,26 @@ static const TypeInfo riscv_cpu_type_infos[] = {
      DEFINE_RISCV_CPU(TYPE_RISCV_CPU_BASE64, TYPE_RISCV_DYNAMIC_CPU,
          .cfg.max_satp_mode = VM_1_10_SV57,
          .misa_mxl_max = MXL_RV64,
+
+        /*  Default extensions as of QEMU 11.1.  */
+        .cfg.ext_zicbom = true,
+        .cfg.ext_zicbop = true,
+        .cfg.ext_zicboz = true,
+        .cfg.ext_zicntr = true,
+        .cfg.ext_zicsr = true,
+        .cfg.ext_zifencei = true,
+        .cfg.ext_zihintntl = true,
+        .cfg.ext_zihintpause = true,
+        .cfg.ext_zihpm = true,
+        .cfg.ext_zawrs = true,
+        .cfg.ext_zfa = true,
+        .cfg.ext_zba = true,
+        .cfg.ext_zbb = true,
+        .cfg.ext_zbc = true,
+        .cfg.ext_zbs = true,
+        .cfg.ext_sstc = true,
+        .cfg.ext_svadu = true,
+        .cfg.ext_svvptc = true,
      ),

DEFINE_RISCV_CPU(TYPE_RISCV_CPU_SIFIVE_E51, TYPE_RISCV_CPU_SIFIVE_E,

diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index 50d9218a75..7575884d7e 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -1553,24 +1553,10 @@ static void cpu_get_multi_ext_cfg(Object *obj, Visitor 
*v, const char *name,
  static void cpu_add_multi_ext_prop(Object *cpu_obj,
                                     const RISCVCPUMultiExtConfig *multi_cfg)
  {
-    bool generic_cpu = riscv_cpu_is_generic(cpu_obj);
-
      object_property_add(cpu_obj, multi_cfg->name, "bool",
                          cpu_get_multi_ext_cfg,
                          cpu_set_multi_ext_cfg,
                          NULL, (void *)&multi_cfg->offset);
-
-    if (!generic_cpu) {
-        return;
-    }
-
-    /*
-     * Set def val directly instead of using
-     * object_property_set_bool() to save the set()
-     * callback hash for user inputs.
-     */
-    isa_ext_update_enabled(RISCV_CPU(cpu_obj), multi_cfg->offset,
-                           multi_cfg->enabled);
  }

static void riscv_cpu_add_multiext_prop_array(Object *obj,