Hi Alistair, On Wed, May 27, 2026 at 8:57 AM Alistair Francis <[email protected]> wrote:
> On Tue, Dec 31, 2024 at 1:28 PM <[email protected]> wrote: > > > > From: Tommy Wu <[email protected]> > > > > The Smrnmi extension adds the 'mnscratch', 'mnepc', 'mncause', > > 'mnstatus' CSRs. > > > > Signed-off-by: Frank Chang <[email protected]> > > Signed-off-by: Tommy Wu <[email protected]> > > Reviewed-by: Alistair Francis <[email protected]> > > --- > > target/riscv/cpu.c | 5 +++ > > target/riscv/cpu.h | 7 ++++ > > target/riscv/cpu_bits.h | 11 ++++++ > > target/riscv/csr.c | 82 +++++++++++++++++++++++++++++++++++++++++ > > 4 files changed, 105 insertions(+) > > > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > > index 58bb5196a8..c5d5c2f7df 100644 > > --- a/target/riscv/cpu.c > > +++ b/target/riscv/cpu.c > > @@ -1127,6 +1127,11 @@ static void riscv_cpu_reset_hold(Object *obj, > ResetType type) > > riscv_trigger_reset_hold(env); > > } > > > > + if (cpu->cfg.ext_smrnmi) { > > + env->rnmip = 0; > > + env->mnstatus = set_field(env->mnstatus, MNSTATUS_NMIE, false); > > + } > > + > > if (kvm_enabled()) { > > kvm_riscv_reset_vcpu(cpu); > > } > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > > index 284b112821..a2cb471b3c 100644 > > --- a/target/riscv/cpu.h > > +++ b/target/riscv/cpu.h > > @@ -486,6 +486,13 @@ struct CPUArchState { > > uint64_t kvm_timer_state; > > uint64_t kvm_timer_frequency; > > #endif /* CONFIG_KVM */ > > + > > + /* RNMI */ > > + target_ulong mnscratch; > > + target_ulong mnepc; > > + target_ulong mncause; /* mncause without bit XLEN-1 set to 1 */ > > + target_ulong mnstatus; > > + target_ulong rnmip; > > These have been added to the wrong part of the struct, they should be > above the comment > > /* Fields from here on are preserved across CPU reset. */ > > Can you fix this up please? > Sure, I can submit a patchset to move these fields above this line. BTW, do we have a plan to support resetting the registers on CPU reset, similar to other architectures? E.g., For ARM, it has struct {} end_reset_fields, and the registers are reset to 0 on CPU reset: https://github.com/qemu/qemu/blob/master/target/arm/cpu.c#L320 Regards, Frank Chang > > Alistair >
