inst_length() can return 0 if 'inst' happens to not match any known encoding (like [1]). Returning 0 is not desirable, even for unknown encodings, given that it will cause a loop in target_disas() later on.
The most recent version of the RISC-V unpriv spec ditched the sophisticated instruction-length encoding. We're now supporting only 16-bit and 32-bit length instructions, where: "All the 32-bit instructions in the base ISA have their lowest two bits set to 11. The optional compressed 16-bit instruction-set extensions have their lowest two bits equal to 00, 01, or 10." So the code is now simpler, never returning 0, and in fact it's the same thing we're already doing in insn_len() from target/riscv/internals.h. Due to include shenarigans we can't use that function in disas/riscv.c, but I believe we can cut ourselves some slack this time and not lose sleep over a 1 line of duplicated logic. We're documenting it though! [1] https://gitlab.com/qemu-project/qemu/-/work_items/3479 Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3479 Signed-off-by: Daniel Henrique Barboza <[email protected]> --- disas/riscv.c | 20 ++------------------ 1 file changed, 2 insertions(+), 18 deletions(-) diff --git a/disas/riscv.c b/disas/riscv.c index d416a4d6b3..fbdb24fcea 100644 --- a/disas/riscv.c +++ b/disas/riscv.c @@ -5057,26 +5057,10 @@ static bool check_constraints(rv_decode *dec, const rvc_constraint *c) return true; } -/* instruction length */ - +/* Same as insn_len() from target/riscv/internals.h */ static size_t inst_length(rv_inst inst) { - /* NOTE: supports maximum instruction size of 64-bits */ - - /* - * instruction length coding - * - * aa - 16 bit aa != 11 - * bbb11 - 32 bit bbb != 111 - * 011111 - 48 bit - * 0111111 - 64 bit - */ - - return (inst & 0b11) != 0b11 ? 2 - : (inst & 0b11100) != 0b11100 ? 4 - : (inst & 0b111111) == 0b011111 ? 6 - : (inst & 0b1111111) == 0b0111111 ? 8 - : 0; + return (inst & 3) == 3 ? 4 : 2; } /* format instruction */ -- 2.43.0
