On Mon, 18 May 2026 at 08:34, Corvin Köhne <[email protected]> wrote:
>
> From: YannickV <[email protected]>
>
> Add CPU clock outs und derive the related domains from the
> base CPU clock ration. This makes the CPU clock domains
> visible and keeps their ratios consistent with the hardware
> clock tree.
>
> We also need to set the reset values during realization to
> ensure CPU clocks are properly enabled at startup. Without
> this, CPU clocks would have a frequency of 0 Hz, which
> causes problems in the a9mpcore timer implementations.
>
> @@ -630,6 +667,9 @@ static void zynq_slcr_realize(DeviceState *dev, Error
> **errp)
> if (s->boot_mode > 0xF) {
> error_setg(errp, "Invalid boot mode %d specified", s->boot_mode);
> }
> +
> + zynq_slcr_reset_init(OBJECT(s), 0);
> + zynq_slcr_compute_clocks_internal(s, clock_get(s->ps_clk));
> }
This doesn't seem right -- devices should not reset themselves
in their realize methods. What exactly goes wrong without this?
This device's reset method's exit phase handler computes the
clock state and propagates it, so devices consuming the
clocks should get the approrpriate information ath that point.
thanks
-- PMM
