Hi; here's an arm pullreq. This is mostly bug fixes; the new features are emulation of a couple of small Arm CPU features.
thanks -- PMM The following changes since commit 2db91528542672cf0db78b3f2cc0e22b36302b38: Merge tag 'pull-vfio-20260527' of https://github.com/legoater/qemu into staging (2026-05-27 14:45:58 -0400) are available in the Git repository at: https://gitlab.com/pm215/qemu.git tags/pull-target-arm-20260529 for you to fetch changes up to 44f2c7f3df0028de7991385f568add12e24aca47: hw/dma/omap_dma: Fix indentation after ifdef removal (2026-05-29 10:18:11 +0100) ---------------------------------------------------------------- target-arm queue: * target/arm: Implement FEAT_CMPBR emulation * target/arm: Implement FEAT_RNG_TRAP emulation * target/arm: Don't assert if 64-bit EL2 AT insn sees a Domain fault * target/arm: SME BFCVT, BFCVTN have "Alternate BFloat16 behaviors" * target/arm: Enable REVD for SVE2.1 * zynq: Various minor bug fixes * hw/misc: Add dummy ZYNQ DDR controller * hw/block/m25p80: Add HAS_SR_TB flag for is25lp016d * hw/dma/omap_dma: Remove unused ifdeffed out code ---------------------------------------------------------------- Jason Wright (2): target/arm: implement FEAT_RNG_TRAP for RNDR/RNDRRS target/arm: advertise FEAT_RNG_TRAP on cortex-max Peter Maydell (5): target/arm: Don't assert if 64-bit EL2 AT insn sees a Domain fault target/arm: SME BFCVT, BFCVTN have "Alternate BFloat16 behaviors" hw/dma/omap_dma: Remove unused ifdeffed out code hw/dma/omap_dma: Fix coding style in omap_dma_transfer_setup() hw/dma/omap_dma: Fix indentation after ifdef removal Richard Henderson (5): target/arm: Enable REVD for SVE2.1 target/arm: Add feature predicate for FEAT_CMPBR target/arm: Implement CB, CBB, CBH target/arm: Implement CB (immediate) target/arm: Enable FEAT_CMPBR for -cpu max YannickV (9): hw/dma/zynq-devcfg: Handle bitstream loading via DMA to 0xffffffff hw/arm/zynq-devcfg: Prevent unintended unlock during initialization hw/dma/zynq: Ensure PCFG_DONE bit remains set to indicate PL is in user mode hw/dma/zynq-devcfg: Simulate dummy PL reset hw/dma/zynq-devcfg: Indicate power-up status of PL hw/misc: Add dummy ZYNQ DDR controller hw/misc/zynq_slcr: Add logic for DCI configuration hw/block/m25p80: Add HAS_SR_TB flag for is25lp016d hw/arm/xilinx_zynq: Split xilinx_zynq into header and implementation files MAINTAINERS | 2 + docs/system/arm/emulation.rst | 2 + hw/arm/Kconfig | 1 + hw/arm/xilinx_zynq.c | 29 ++- hw/block/m25p80.c | 3 +- hw/dma/omap_dma.c | 247 ++++++++--------------- hw/dma/xlnx-zynq-devcfg.c | 27 ++- hw/misc/Kconfig | 3 + hw/misc/meson.build | 1 + hw/misc/xlnx-zynq-ddrc.c | 421 +++++++++++++++++++++++++++++++++++++++ hw/misc/zynq_slcr.c | 31 +++ include/hw/arm/xilinx_zynq.h | 30 +++ include/hw/misc/xlnx-zynq-ddrc.h | 147 ++++++++++++++ linux-user/aarch64/elfload.c | 1 + target/arm/cpu-features.h | 10 + target/arm/helper.c | 58 +++++- target/arm/internals.h | 10 + target/arm/tcg/a64.decode | 11 + target/arm/tcg/cpu64.c | 3 +- target/arm/tcg/translate-a64.c | 86 ++++++++ target/arm/tcg/translate-sme.c | 4 +- target/arm/tcg/translate-sve.c | 3 +- 22 files changed, 939 insertions(+), 191 deletions(-) create mode 100644 hw/misc/xlnx-zynq-ddrc.c create mode 100644 include/hw/arm/xilinx_zynq.h create mode 100644 include/hw/misc/xlnx-zynq-ddrc.h
