Register AccelCPUClass::cpu_target_realize as
riscv_tcg_ops::cpu_realize. RISCV's ACCEL_CPU_NAME("tcg")
TypeInfo is now empty, remove it.Signed-off-by: Philippe Mathieu-Daudé <[email protected]> --- target/riscv/tcg/tcg-cpu.c | 24 ++---------------------- 1 file changed, 2 insertions(+), 22 deletions(-) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 703c2d9bd0a..c885af6c03f 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -30,7 +30,6 @@ #include "qemu/accel.h" #include "qemu/error-report.h" #include "qemu/log.h" -#include "accel/accel-cpu-target.h" #include "accel/tcg/cpu-ops.h" #include "tcg/tcg.h" #ifndef CONFIG_USER_ONLY @@ -269,6 +268,7 @@ static vaddr riscv_pointer_wrap(CPUState *cs, int mmu_idx, #endif static void riscv_tcg_cpu_instance_init(CPUState *cs); +static bool riscv_tcg_cpu_realize(CPUState *cs, Error **errp); const TCGCPUOps riscv_tcg_ops = { .mttcg_supported = true, @@ -276,6 +276,7 @@ const TCGCPUOps riscv_tcg_ops = { .initialize = riscv_translate_init, .cpu_instance_init = riscv_tcg_cpu_instance_init, + .cpu_realize = riscv_tcg_cpu_realize, .translate_code = riscv_translate_code, .get_tb_cpu_state = riscv_get_tb_cpu_state, .synchronize_from_tb = riscv_cpu_synchronize_from_tb, @@ -1676,24 +1677,3 @@ static void riscv_tcg_cpu_instance_init(CPUState *cs) riscv_init_max_cpu_extensions(obj); } } - -static void riscv_tcg_cpu_accel_class_init(ObjectClass *oc, const void *data) -{ - AccelCPUClass *acc = ACCEL_CPU_CLASS(oc); - - acc->cpu_target_realize = riscv_tcg_cpu_realize; -} - -static const TypeInfo riscv_tcg_cpu_accel_type_info = { - .name = ACCEL_CPU_NAME("tcg"), - - .parent = TYPE_ACCEL_CPU, - .class_init = riscv_tcg_cpu_accel_class_init, - .abstract = true, -}; - -static void riscv_tcg_cpu_accel_register_types(void) -{ - type_register_static(&riscv_tcg_cpu_accel_type_info); -} -type_init(riscv_tcg_cpu_accel_register_types); -- 2.53.0
