The DPM0-3 and CPM0-3 entries had wrong addresses and were never used. Replace with the correct per-protection-set enable bitmask registers (CPXE, DPRE, DPWE) per the TriCore architecture manual.
Signed-off-by: Parthiban Nallathambi <[email protected]> --- target/tricore/csfr.h.inc | 20 ++++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/target/tricore/csfr.h.inc b/target/tricore/csfr.h.inc index cdfaf1d662..24d8310947 100644 --- a/target/tricore/csfr.h.inc +++ b/target/tricore/csfr.h.inc @@ -83,14 +83,18 @@ A(0xDC10, CPR3_2L, TRICORE_FEATURE_13) A(0xDC14, CPR3_2U, TRICORE_FEATURE_13) A(0xDC18, CPR3_3L, TRICORE_FEATURE_13) A(0xDC1C, CPR3_3U, TRICORE_FEATURE_13) -A(0xE000, DPM0, TRICORE_FEATURE_13) -A(0xE080, DPM1, TRICORE_FEATURE_13) -A(0xE100, DPM2, TRICORE_FEATURE_13) -A(0xE180, DPM3, TRICORE_FEATURE_13) -A(0xE200, CPM0, TRICORE_FEATURE_13) -A(0xE280, CPM1, TRICORE_FEATURE_13) -A(0xE300, CPM2, TRICORE_FEATURE_13) -A(0xE380, CPM3, TRICORE_FEATURE_13) +A(0xE000, CPXE_0, TRICORE_FEATURE_13) +A(0xE004, CPXE_1, TRICORE_FEATURE_13) +A(0xE008, CPXE_2, TRICORE_FEATURE_13) +A(0xE00C, CPXE_3, TRICORE_FEATURE_13) +A(0xE010, DPRE_0, TRICORE_FEATURE_13) +A(0xE014, DPRE_1, TRICORE_FEATURE_13) +A(0xE018, DPRE_2, TRICORE_FEATURE_13) +A(0xE01C, DPRE_3, TRICORE_FEATURE_13) +A(0xE020, DPWE_0, TRICORE_FEATURE_13) +A(0xE024, DPWE_1, TRICORE_FEATURE_13) +A(0xE028, DPWE_2, TRICORE_FEATURE_13) +A(0xE02C, DPWE_3, TRICORE_FEATURE_13) /* memory management registers */ A(0x8000, MMU_CON, TRICORE_FEATURE_13) A(0x8004, MMU_ASI, TRICORE_FEATURE_13) -- 2.47.3
