On 4/17/26 05:28, Jamin Lin wrote:
AST2700 provides a single FMC controller shared by the main CA35 processor
(PSP) and the SSP/TSP coprocessors.
From the PSP perspective, the FMC controller is memory-mapped at
0x14000000–0x140000FF. The SSP and TSP access the same controller through
a different address window at 0x74000000–0x740000FF.
This change allows the SSP and TSP SoC models to reference the existing
PSP FMC instance instead of creating independent controllers. An MMIO
alias is added in the SSP and TSP address spaces to map their FMC access
window to the shared FMC device.
This ensures consistent FMC state across PSP, SSP, and TSP and matches
the AST2700 hardware design.
Signed-off-by: Jamin Lin <[email protected]>
---
include/hw/arm/aspeed_coprocessor.h | 2 ++
hw/arm/aspeed_ast27x0-fc.c | 4 ++++
hw/arm/aspeed_ast27x0-ssp.c | 10 ++++++++++
hw/arm/aspeed_ast27x0-tsp.c | 10 ++++++++++
4 files changed, 26 insertions(+)
diff --git a/include/hw/arm/aspeed_coprocessor.h
b/include/hw/arm/aspeed_coprocessor.h
index 4db995d251..2460a11401 100644
--- a/include/hw/arm/aspeed_coprocessor.h
+++ b/include/hw/arm/aspeed_coprocessor.h
@@ -50,7 +50,9 @@ struct Aspeed27x0CoprocessorState {
ARMv7MState armv7m;
MemoryRegion scu_alias;
+ MemoryRegion fmc_alias;
Aspeed2700SCUState *scu;
+ AspeedSMCState *fmc;
};
#define TYPE_ASPEED27X0SSP_COPROCESSOR "aspeed27x0ssp-coprocessor"
diff --git a/hw/arm/aspeed_ast27x0-fc.c b/hw/arm/aspeed_ast27x0-fc.c
index 62bd6a0568..56dd86e2c2 100644
--- a/hw/arm/aspeed_ast27x0-fc.c
+++ b/hw/arm/aspeed_ast27x0-fc.c
@@ -161,6 +161,8 @@ static bool ast2700fc_ssp_init(MachineState *machine, Error
**errp)
OBJECT(&psp->sram), &error_abort);
object_property_set_link(OBJECT(&s->ssp), "scu",
OBJECT(&s->ca35.scu), &error_abort);
I would change ast2700fc_ssp_init() and ast2700fc_tsp_init() to use
a AspeedSoCState argument and not a MachineState. This to reflect
that the AspeedSoCState *needs* to be realized before the coprocessors.
A comment is worth adding.
+ object_property_set_link(OBJECT(&s->ssp), "fmc",
+ OBJECT(&psp->fmc), &error_abort);
if (!qdev_realize(DEVICE(&s->ssp), NULL, errp)) {
return false;
}
@@ -193,6 +195,8 @@ static bool ast2700fc_tsp_init(MachineState *machine, Error
**errp)
OBJECT(&psp->sram), &error_abort);
object_property_set_link(OBJECT(&s->tsp), "scu",
OBJECT(&s->ca35.scu), &error_abort);
+ object_property_set_link(OBJECT(&s->tsp), "fmc",
+ OBJECT(&psp->fmc), &error_abort);
if (!qdev_realize(DEVICE(&s->tsp), NULL, errp)) {
return false;
}
diff --git a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm/aspeed_ast27x0-ssp.c
index 0500c02755..bfd6fe4485 100644
--- a/hw/arm/aspeed_ast27x0-ssp.c
+++ b/hw/arm/aspeed_ast27x0-ssp.c
@@ -26,6 +26,7 @@ static const hwaddr aspeed_soc_ast27x0ssp_memmap[] = {
[ASPEED_DEV_TIMER1] = 0x72C10000,
[ASPEED_DEV_UART4] = 0x72C1A000,
[ASPEED_DEV_IPC0] = 0x72C1C000,
+ [ASPEED_DEV_FMC] = 0x74000000,
[ASPEED_DEV_SCUIO] = 0x74C02000,
[ASPEED_DEV_INTCIO] = 0x74C18000,
[ASPEED_DEV_UART0] = 0x74C33000,
@@ -256,6 +257,13 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState
*dev_soc, Error **errp)
sysbus_connect_irq(SYS_BUS_DEVICE(s->uart), 0,
aspeed_soc_ast27x0ssp_get_irq(s, s->uart_dev));
Please check that a->fmc is set :
if (!a->fmc) {
error_setg(errp, TYPE_ASPEED27X0SSP_COPROCESSOR ": 'fmc' link not set");
return;
}
+ /* FMC */
+ memory_region_init_alias(&a->fmc_alias, OBJECT(a), "fmc.alias",
+ &a->fmc->mmio, 0,
+ memory_region_size(&a->fmc->mmio));
Isn't that too big for 0x14000000–0x140000FF ?
What about the flash contents window ? Is there one in the coprocessor
socs ? Is is unimplemented ?
+ memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_FMC],
+ &a->fmc_alias);
+
aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->timerctrl),
"aspeed.timerctrl",
sc->memmap[ASPEED_DEV_TIMER1], 0x200);
@@ -273,6 +281,8 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState
*dev_soc, Error **errp)
static const Property aspeed_27x0_coprocessor_properties[] = {
DEFINE_PROP_LINK("scu", Aspeed27x0CoprocessorState, scu,
TYPE_ASPEED_2700_SCU, Aspeed2700SCUState *),
+ DEFINE_PROP_LINK("fmc", Aspeed27x0CoprocessorState, fmc, TYPE_ASPEED_SMC,
+ AspeedSMCState *),
};
static void aspeed_soc_ast27x0ssp_class_init(ObjectClass *klass,
diff --git a/hw/arm/aspeed_ast27x0-tsp.c b/hw/arm/aspeed_ast27x0-tsp.c
index 4da4741d8a..166dcb14ed 100644
--- a/hw/arm/aspeed_ast27x0-tsp.c
+++ b/hw/arm/aspeed_ast27x0-tsp.c
@@ -26,6 +26,7 @@ static const hwaddr aspeed_soc_ast27x0tsp_memmap[] = {
[ASPEED_DEV_TIMER1] = 0x72C10000,
[ASPEED_DEV_UART4] = 0x72C1A000,
[ASPEED_DEV_IPC0] = 0x72C1C000,
+ [ASPEED_DEV_FMC] = 0x74000000,
[ASPEED_DEV_SCUIO] = 0x74C02000,
[ASPEED_DEV_INTCIO] = 0x74C18000,
[ASPEED_DEV_UART0] = 0x74C33000,
@@ -253,6 +254,13 @@ static void aspeed_soc_ast27x0tsp_realize(DeviceState
*dev_soc, Error **errp)
sysbus_connect_irq(SYS_BUS_DEVICE(s->uart), 0,
aspeed_soc_ast27x0tsp_get_irq(s, s->uart_dev));
+ /* FMC */
+ memory_region_init_alias(&a->fmc_alias, OBJECT(a), "fmc.alias",
+ &a->fmc->mmio, 0,
+ memory_region_size(&a->fmc->mmio));
+ memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_FMC],
+ &a->fmc_alias);
+
aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->timerctrl),
"aspeed.timerctrl",
sc->memmap[ASPEED_DEV_TIMER1], 0x200);
@@ -270,6 +278,8 @@ static void aspeed_soc_ast27x0tsp_realize(DeviceState
*dev_soc, Error **errp)
static const Property aspeed_27x0_coprocessor_properties[] = {
DEFINE_PROP_LINK("scu", Aspeed27x0CoprocessorState, scu,
TYPE_ASPEED_2700_SCU, Aspeed2700SCUState *),
+ DEFINE_PROP_LINK("fmc", Aspeed27x0CoprocessorState, fmc, TYPE_ASPEED_SMC,
+ AspeedSMCState *),
};
static void aspeed_soc_ast27x0tsp_class_init(ObjectClass *klass,
