Peter Maydell 於 2026/5/26 下午 10:18 寫道:
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On Thu, 30 Apr 2026 at 10:19, Kuan-Jui Chiu <[email protected]> wrote:
This patch add a new model for Cadence GPIO controller which
supports 32 pins and interrupts for level-triggered/edge-triggered type on
input pins.
Also define new trace functions for analysis purpose and new configuration to
enable this model.
Signed-off-by: Kuan-Jui Chiu <[email protected]>
---
hw/gpio/Kconfig | 3 +
hw/gpio/cadence_gpio.c | 301 +++++++++++++++++++++++++++++++++
hw/gpio/meson.build | 1 +
hw/gpio/trace-events | 5 +
include/hw/gpio/cadence_gpio.h | 55 ++++++
5 files changed, 365 insertions(+)
create mode 100644 hw/gpio/cadence_gpio.c
create mode 100644 include/hw/gpio/cadence_gpio.h
diff --git a/hw/gpio/Kconfig b/hw/gpio/Kconfig
index a209294c20..fcc7c70bd5 100644
--- a/hw/gpio/Kconfig
+++ b/hw/gpio/Kconfig
@@ -30,3 +30,6 @@ config PCF8574
config ZAURUS_SCOOP
bool
+
+config CADENCE_GPIO
+ bool
diff --git a/hw/gpio/cadence_gpio.c b/hw/gpio/cadence_gpio.c
new file mode 100644
index 0000000000..2410753abc
--- /dev/null
+++ b/hw/gpio/cadence_gpio.c
@@ -0,0 +1,301 @@
+/*
+ * Cadence GPIO emulation.
+ *
+ * Author: Kuan-Jui Chiu <[email protected]>
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
Is there an available data sheet for this device?
What is the actual device model name? "Cadence GPIO" is
extremely vague...
Axiado SoC is using Cadence IP for GPIO controller
I am afraid of that I can't share the data sheet publicly
Here is the link to Cadence official website
Artisan Foundation and Mixed‑Signal IP | Cadence
<https://www.cadence.com/en_US/home/tools/silicon-solutions/artisan-ip.html#gpio>
thanks
-- PMM
