Re: [PATCH v4 1/2] target/riscv: Add the implied rule for G extension

[Alistair Francis]

On Thu, May 28, 2026 at 3:43 PM <frank.ch...@sifive.com> wrote:
>
> From: Jim Shu <jim....@sifive.com>
>
> Add the missing implied rule from G to imafd_zicsr_zifencei.
> We can also remove the auto-enables in riscv_cpu_validate_g() as
> IMAFD, Zicsr, Zifencei extensions can be enabled by the implied rule.
>
> Signed-off-by: Jim Shu <jim....@sifive.com>
> Reviewed-by: Frank Chang <frank.ch...@sifive.com>

Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>

Alistair

> ---
>  target/riscv/cpu.c         | 14 +++++++++++++-
>  target/riscv/tcg/tcg-cpu.c | 21 ++++-----------------
>  2 files changed, 17 insertions(+), 18 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 952e34fdf55..4246fb87c64 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -2094,6 +2094,18 @@ static RISCVCPUImpliedExtsRule RVV_IMPLIED = {
>      },
>  };
>
> +static RISCVCPUImpliedExtsRule RVG_IMPLIED = {
> +    .is_misa = true,
> +    .ext = RVG,
> +    .implied_misa_exts = RVI | RVM | RVA | RVF | RVD,
> +    .implied_multi_exts = {
> +        CPU_CFG_OFFSET(ext_zicsr),
> +        CPU_CFG_OFFSET(ext_zifencei),
> +
> +        RISCV_IMPLIED_EXTS_RULE_END
> +    },
> +};
> +
>  static RISCVCPUImpliedExtsRule ZCB_IMPLIED = {
>      .ext = CPU_CFG_OFFSET(ext_zcb),
>      .implied_multi_exts = {
> @@ -2501,7 +2513,7 @@ static RISCVCPUImpliedExtsRule ZVFBFA_IMPLIED = {
>
>  RISCVCPUImpliedExtsRule *riscv_misa_ext_implied_rules[] = {
>      &RVA_IMPLIED, &RVD_IMPLIED, &RVF_IMPLIED,
> -    &RVM_IMPLIED, &RVV_IMPLIED, NULL
> +    &RVM_IMPLIED, &RVV_IMPLIED, &RVG_IMPLIED, NULL
>  };
>
>  RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[] = {
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index 7e964e8f1aa..66ac011c54d 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -496,30 +496,17 @@ static void riscv_cpu_validate_g(RISCVCPU *cpu)
>              continue;
>          }
>
> -        if (!cpu_misa_ext_is_user_set(bit)) {
> -            riscv_cpu_write_misa_bit(cpu, bit, true);
> -            continue;
> -        }
> -
>          if (send_warn) {
>              warn_report(warn_msg, riscv_get_misa_ext_name(bit));
>          }
>      }
>
> -    if (!cpu->cfg.ext_zicsr) {
> -        if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zicsr))) {
> -            cpu->cfg.ext_zicsr = true;
> -        } else if (send_warn) {
> -            warn_report(warn_msg, "zicsr");
> -        }
> +    if (!cpu->cfg.ext_zicsr && send_warn) {
> +        warn_report(warn_msg, "zicsr");
>      }
>
> -    if (!cpu->cfg.ext_zifencei) {
> -        if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zifencei))) {
> -            cpu->cfg.ext_zifencei = true;
> -        } else if (send_warn) {
> -            warn_report(warn_msg, "zifencei");
> -        }
> +    if (!cpu->cfg.ext_zifencei && send_warn) {
> +        warn_report(warn_msg, "zifencei");
>      }
>  }
>
> --
> 2.43.0
>
>