On Sat, May 30, 2026 at 8:22 PM Abhigyan Kumar <[email protected]> wrote: > > Citing the RISC-V specification: > > "The vector fixed-point rounding-mode register holds a two-bit > read-write rounding-mode field in the least-significant bits > (vxrm[1:0]). The upper bits, vxrm[XLEN-1:2], should be written as > zeros." > > QEMU wrote full value into env->vxrm causing read of upper bits too. > Used existing macros for bit-masking. Previous had a hard-coded value. > > Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3470 > Signed-off-by: Abhigyan Kumar <[email protected]>
Reviewed-by: Alistair Francis <[email protected]> Alistair > --- > target/riscv/csr.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index 5514e0f45..7b98d66db 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -977,7 +977,7 @@ static RISCVException write_vxrm(CPURISCVState *env, int > csrno, > #if !defined(CONFIG_USER_ONLY) > env->mstatus |= MSTATUS_VS; > #endif > - env->vxrm = val; > + env->vxrm = val & (VCSR_VXRM >> VCSR_VXRM_SHIFT); > return RISCV_EXCP_NONE; > } > > -- > 2.54.0 > >
