Hi Clement, >-----Original Message----- >From: Clément MATHIEU--DRIF <[email protected]> >Subject: Re: [PATCH v6 11/17] intel_iommu_accel: Handle PASID entry addition >for >pc_inv_dsc request > > >On Wed, 2026-05-27 at 01:46 -0400, Zhenzhong Duan wrote: >> Caution: External email. Do not open attachments or click links, unless this >> email >comes from a known sender and you know the content is safe. >> >> >> Structure VTDAddressSpace includes some elements suitable for emulated >> device and passthrough device without PASID, e.g., address space, >> different memory regions, etc, it is also protected by vtd iommu lock, >> all these are useless and become a burden for passthrough device with >> PASID. >> >> When there are lots of PASIDs used in one device, the AS and MRs are >> all registered to memory core and impact the whole system performance. >> >> So instead of using VTDAddressSpace to cache pasid entry for each pasid >> of a passthrough device, we define a light weight structure >> VTDAccelPASIDCacheEntry with only necessary elements for each pasid. We >> will use this struct as a parameter to conduct binding/unbinding to >> nested hwpt and to record the current bound nested hwpt. It's also >> designed to support IOMMU_NO_PASID. >> >> VTDAccelPASIDCacheEntry is designed to only be used in intel_iommu_accel.c, > >For consistency with next line: >s@intel_iommu_accel.c@hw/i386/intel_iommu_accel.c
Sure, will do. Thanks Zhenzhong
