Hi Peter,
On 29/5/26 19:46, Peter Maydell wrote:
We implement the fw_cfg device for more architectures and machines
that we let on about in our documentation. Luckily most of the new
ones (notably riscv and loongarch) have followed the straightforward
layout that the Arm virt board picked.
Restructure the documentation to present this as the "standard"
layout, followed by the other layouts used by various other boards
for historical reasons. This adds PA-RISC, SPARC, PPC and MIPS.
Signed-off-by: Peter Maydell <[email protected]>
---
docs/specs/fw_cfg.rst | 28 ++++++++++++++++++++++++----
1 file changed, 24 insertions(+), 4 deletions(-)
diff --git a/docs/specs/fw_cfg.rst b/docs/specs/fw_cfg.rst
index 31ae31576b..7e2fe0851d 100644
--- a/docs/specs/fw_cfg.rst
+++ b/docs/specs/fw_cfg.rst
@@ -84,15 +84,35 @@ increasing address order, similar to memcpy().
Register Locations
------------------
+For a memory-mapped fw_cfg device, the standard register layout is:
+
+ * base address : Data Register (64 bit)
+ * base address + 8 : Selector Register (16 bit)
+ * base address + 16 : DMA Address Register (64 bit)
+
+Some architectures or machines have a different layout for historical reasons:
+
x86, x86_64
* Selector Register IOport: 0x510
* Data Register IOport: 0x511
* DMA Address IOport: 0x514
+64-bit SPARC:
+ * base address : Selector Register (16 bit)
+ * base address + 1 : Data Register (8 bit)
IIUC they have both the same base address.
