On Fri, 29 May 2026 at 09:29, Alex Bennée <[email protected]> wrote:
>
> Remove the restrictions that make this a M-profile only operation and
> enable the instructions for all Arm profiles.
>
> Reviewed-by: Richard Henderson <[email protected]>
> Signed-off-by: Alex Bennée <[email protected]>
>
> ---
> v2
> - fix alignment in a32.decode
> - set bool directly, defend with QEMU_BUILD_BUG_ON
> - s/instructions/profiles/
> - share get_event_reg between translate/translate-a64
> diff --git a/target/arm/tcg/a32.decode b/target/arm/tcg/a32.decode
> index f2ca4809495..547aa2b1490 100644
> --- a/target/arm/tcg/a32.decode
> +++ b/target/arm/tcg/a32.decode
> @@ -192,9 +192,8 @@ SMULTT .... 0001 0110 .... 0000 .... 1110 ....
> @rd0mn
> WFE ---- 0011 0010 0000 1111 ---- 0000 0010
> WFI ---- 0011 0010 0000 1111 ---- 0000 0011
>
> - # TODO: Implement SEV, SEVL; may help SMP performance.
> - # SEV ---- 0011 0010 0000 1111 ---- 0000 0100
> - # SEVL ---- 0011 0010 0000 1111 ---- 0000 0101
> + SEV ---- 0011 0010 0000 1111 ---- 0000 0100
> + SEVL ---- 0011 0010 0000 1111 ---- 0000 0101
>
> ESB ---- 0011 0010 0000 1111 ---- 0001 0000
> ]
> diff --git a/target/arm/tcg/t16.decode b/target/arm/tcg/t16.decode
> index 778fbf16275..9a8f89538ac 100644
> --- a/target/arm/tcg/t16.decode
> +++ b/target/arm/tcg/t16.decode
> @@ -228,10 +228,8 @@ REVSH 1011 1010 11 ... ... @rdm
> WFE 1011 1111 0010 0000
> WFI 1011 1111 0011 0000
>
> - # M-profile SEV is implemented.
> - # TODO: Implement SEV for other profiles, and SEVL for all profiles; may
> help SMP performance.
> SEV 1011 1111 0100 0000
> - # SEVL 1011 1111 0101 0000
> + SEVL 1011 1111 0101 0000
> # The canonical nop has the second nibble as 0000, but the whole of the
> # rest of the space is a reserved hint, behaves as nop.
> diff --git a/target/arm/tcg/t32.decode b/target/arm/tcg/t32.decode
> index 49b8d0037ec..8ae277fe112 100644
> --- a/target/arm/tcg/t32.decode
> +++ b/target/arm/tcg/t32.decode
> @@ -369,10 +369,8 @@ CLZ 1111 1010 1011 ---- 1111 .... 1000 ....
> @rdm
> WFE 1111 0011 1010 1111 1000 0000 0000 0010
> WFI 1111 0011 1010 1111 1000 0000 0000 0011
>
> - # M-profile SEV is implemented.
> - # TODO: Implement SEV for other profiles, and SEVL for all profiles;
> may help SMP performance.
> SEV 1111 0011 1010 1111 1000 0000 0000 0100
> - # SEVL 1111 0011 1010 1111 1000 0000 0000 0101
> + SEVL 1111 0011 1010 1111 1000 0000 0000 0101
> ESB 1111 0011 1010 1111 1000 0000 0001 0000
> ]
> diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c
> index c744b163453..e1e5539f571 100644
> --- a/target/arm/tcg/translate.c
> +++ b/target/arm/tcg/translate.c
> @@ -3246,17 +3246,20 @@ static bool trans_YIELD(DisasContext *s, arg_YIELD *a)
> static bool trans_SEV(DisasContext *s, arg_SEV *a)
> {
> /*
> - * Currently SEV is a NOP for non-M-profile and in user-mode emulation.
> - * For system-mode M-profile, it sets the event register.
> + * SEV is a NOP for user-mode emulation.
> */
> #ifndef CONFIG_USER_ONLY
> - if (arm_dc_feature(s, ARM_FEATURE_M)) {
> - gen_helper_sev(tcg_env);
> - }
> + gen_helper_sev(tcg_env);
> #endif
The AArch32 SEV encodings are only SEV for M-profile and for
Armv7A and above -- for v6T2 and earlier they are NOP hints.
We need a feature-check here.
> return true;
> }
>
> +static bool trans_SEVL(DisasContext *s, arg_SEV *a)
> +{
> + gen_event_reg();
> + return true;
The SEVL encodings only exist for v8A -- they are unallocated
must-NOP hints for M-profile and v7A and earlier. We need a
feature-check here.
> +}
> +
> static bool trans_WFE(DisasContext *s, arg_WFE *a)
thanks
-- PMM
