Greetings, In this new version a lot of changes were made. Some of them based in the reviews from v7 [1], others from a more in-depth review I did with Drew Jones.
The most notable change is the TPM support, missing from the previous versions. Turns out this is a must have for the server-ref spec 1.0 and we can't miss out on it. TPM support is added in patch 5, while patch 6 changes the existing testcase to support TPM. Adding TPM support required the addition of a platform bus, and with it I realized that the board was running an old version of aplic and imisics DT that were copied from the 'virt' board. With this realization I did some fine tuning in other DT problems that the board had. Finally, in patch 2, I'm following Icenowy's suggestion and the riscv-server-ref CPU is now based on the profile engine. This change fixed the satp issue we were having in v7 without the need for additional changes in the base code (that I'll end up sending anyway). I liked the end result but I'm ready to hear different opinions. There was also another notable change in patch 2, based on another realization when reading the riscv-server-ref spec: we don't have enough debug triggers. The spec requires at least 11, RISC-V CPUs has 2 hardcoded triggers per default. I am solving this in the base code with additional changes [2], and after that we're now able to add 11 triggers to riscv-server-ref to be spec compliant. Additional triggers can be set via a new property called 'num-triggers' - see [2] for more info. What we're missing here is an EDK2 compliant image. I am aware that there is an upstream effort to make this image available, but I reckon such effort is also reliant on this work availability. I guess we'll keep pushing new revisions of this work as long as needed until it goes upstream, and update tests/docs with the EDK2 information when we have a eligible image. This series is now dependant on two not yet upstreamed work: - Chao Liu's series "[PATCH v6 0/7] riscv: add initial sdext support" - "[PATCH v2 0/2] target/riscv: parametrize debug trigger number" For easier consumption this work is available at this branch: https://gitlab.com/danielhb/qemu/-/tree/riscv-server-ref_v8 Changes from v7: - patch 2: - create riscv-server-ref using the profile backend - patch 3: - fix aplic, imsics and iommu-map DT generation - patch 4: - change test_boot_linux_test to use a PCIe AHCI disk instead of virtio - patch 5 (new): - add platform bus to support TPM (tpm-tis) devices - patch 6 (new): - change riscv-server-ref linux tests to test TPM devices if the host has 'swtpm' support - patch 7 (former 5) - add additional information about TPM support and command line with AHCI disk - v7 link: https://lore.kernel.org/qemu-devel/[email protected]/ [1] https://lore.kernel.org/qemu-devel/[email protected]/ [2] https://lore.kernel.org/qemu-devel/[email protected]/ Daniel Henrique Barboza (6): target/riscv/cpu.c: remove 'bare' condition for .profile target/riscv: add riscv-server-ref CPU tests/functional/riscv64: add riscv-server-ref tests hw/riscv/server_platform_ref.c: add platform bus and TPM support tests/functional/riscv64: add riscv-server-ref TPM selftest docs: add riscv-server-ref.rst Fei Wu (1): hw/riscv: server platform reference machine configs/devices/riscv64-softmmu/default.mak | 1 + docs/system/riscv/riscv-server-ref.rst | 62 + docs/system/target-riscv.rst | 1 + hw/riscv/Kconfig | 16 + hw/riscv/meson.build | 1 + hw/riscv/server_platform_ref.c | 1477 +++++++++++++++++++ target/riscv/cpu-qom.h | 1 + target/riscv/cpu.c | 32 +- tests/functional/riscv64/meson.build | 2 + tests/functional/riscv64/test_opensbi.py | 4 + tests/functional/riscv64/test_server_ref.py | 88 ++ 11 files changed, 1684 insertions(+), 1 deletion(-) create mode 100644 docs/system/riscv/riscv-server-ref.rst create mode 100644 hw/riscv/server_platform_ref.c create mode 100755 tests/functional/riscv64/test_server_ref.py -- 2.43.0
