From: Brian Cain <[email protected]> Add cpu execution mode (user/supervisor/guest), MMU index, and next_PC to DisasContext and translation state. Declare the MMU_INDEX bit field in TB_FLAGS and use it to propagate the mmu index into translations.
Reviewed-by: Taylor Simpson <[email protected]> Reviewed-by: Pierrick Bouvier <[email protected]> Signed-off-by: Brian Cain <[email protected]> --- target/hexagon/cpu.h | 22 +++++++++++++++++++++- target/hexagon/cpu.c | 1 + target/hexagon/translate.c | 2 +- 3 files changed, 23 insertions(+), 2 deletions(-) diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index ddf6da78c18..7ba1d3047df 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -49,8 +49,26 @@ #define VSTORES_MAX 2 #define CPU_RESOLVING_TYPE TYPE_HEXAGON_CPU +#ifndef CONFIG_USER_ONLY +#define CPU_INTERRUPT_SWI CPU_INTERRUPT_TGT_INT_0 + +#define HEX_CPU_MODE_USER 1 +#define HEX_CPU_MODE_GUEST 2 +#define HEX_CPU_MODE_MONITOR 3 + +#define HEX_EXE_MODE_OFF 1 +#define HEX_EXE_MODE_RUN 2 +#define HEX_EXE_MODE_WAIT 3 +#define HEX_EXE_MODE_DEBUG 4 +#endif + +#define MMU_USER_IDX 0 +#ifndef CONFIG_USER_ONLY +#define MMU_GUEST_IDX 1 +#define MMU_KERNEL_IDX 2 + +#endif -#define MMU_USER_IDX 0 #define HEXAGON_CPU_IRQ_0 0 #define HEXAGON_CPU_IRQ_1 1 @@ -112,6 +130,7 @@ typedef struct CPUArchState { uint32_t threadId; uint64_t t_cycle_count; #endif + uint32_t next_PC; target_ulong new_value_usr; MemLog mem_log_stores[STORES_MAX]; @@ -164,6 +183,7 @@ struct ArchCPU { #include "cpu_bits.h" FIELD(TB_FLAGS, IS_TIGHT_LOOP, 0, 1) +FIELD(TB_FLAGS, MMU_INDEX, 1, 3) FIELD(TB_FLAGS, PCYCLE_ENABLED, 4, 1) G_NORETURN void hexagon_raise_exception_err(CPUHexagonState *env, diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 0773ef8fe79..626100d43fd 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -307,6 +307,7 @@ static void hexagon_cpu_reset_hold(Object *obj, ResetType type) memset(env->t_sreg, 0, sizeof(uint32_t) * NUM_SREGS); memset(env->greg, 0, sizeof(uint32_t) * NUM_GREGS); env->wait_next_pc = 0; + env->next_PC = 0; #endif env->cause_code = HEX_EVENT_NONE; } diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index ed96d9a66b3..ce5bbe92d5d 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -988,7 +988,7 @@ static void hexagon_tr_init_disas_context(DisasContextBase *dcbase, HexagonCPU *hex_cpu = env_archcpu(cpu_env(cs)); uint32_t hex_flags = dcbase->tb->flags; - ctx->mem_idx = MMU_USER_IDX; + ctx->mem_idx = FIELD_EX32(hex_flags, TB_FLAGS, MMU_INDEX); ctx->num_packets = 0; ctx->num_insns = 0; ctx->num_hvx_insns = 0; -- 2.34.1
