This is Part 2 of the hexagon system emulation (sysemu) patch series,
building on the infrastructure from Part 1 to implement the runtime
helpers and CPU operations needed for full-system emulation.
This part adds:
- Helper implementations for system instructions: swi, cswi,
iassign, start/stop, wait/resume, setprio, resched
- SSR (System Status Register) modification and exe mode support
- TLB operations: tlb_fill, tlb_entry_get_perm
- Interrupt handling: exec_interrupt, set_irq, software interrupt
- Stack overflow exception (fFRAMECHECK / FRAMELIMIT check)
- CPU execution support: cpu_exec_reset, pointer_wrap, sysemu_ops
- Translation support: pkt_ends_tb, implicit sysreg writes, next_PC
- System/guest register name definitions
- TCG overrides for transfer and load_phys instructions
- Guest register reading functionality
Changes since v5:
- Rebased onto Part 1 v8 (no functional changes in Part 2)
Previous versions:
v5:
https://lore.kernel.org/qemu-devel/[email protected]/
v4:
https://lore.kernel.org/qemu-devel/[email protected]/
v3:
https://lore.kernel.org/qemu-devel/[email protected]/
v2:
https://lore.kernel.org/qemu-devel/[email protected]/
v1:
https://lore.kernel.org/qemu-devel/[email protected]/
Brian Cain (26):
target/hexagon: Implement {c,}swi helpers
target/hexagon: Implement iassign{r,w} helpers
target/hexagon: Implement start/stop helpers, soft reset
target/hexagon: Implement {g,s}etimask helpers
target/hexagon: Implement wait helper
target/hexagon: Implement get_exe_mode()
target/hexagon: Implement hex_tlb_entry_get_perm()
target/hexagon: Implement software interrupt
target/hexagon: Implement stack overflow exception
target/hexagon: Implement exec_interrupt, set_irq
target/hexagon: Implement hexagon_tlb_fill()
target/hexagon: Implement siad inst
target/hexagon: Implement hexagon_resume_threads()
target/hexagon: Implement setprio, resched
target/hexagon: Add sysemu_ops, cpu_get_phys_page_debug()
target/hexagon: extend hexagon_cpu_mmu_index() for sysemu
target/hexagon: Decode trap1, rte as COF
target/hexagon: Implement modify_ssr, resched, pending_interrupt
target/hexagon: Add pkt_ends_tb to translation
target/hexagon: Add next_PC, {s,g}reg writes
target/hexagon: Add implicit sysreg writes
target/hexagon: Define system, guest reg names
target/hexagon: Add k0 {un,}lock
target/hexagon: Add PC to raise_exception, use fTRAP() helper
target/hexagon: Add TCG overrides for transfer insts
target/hexagon: Add support for loadw_phys
Matheus Tavares Bernardino (2):
target/hexagon: add simple cpu_exec_reset and pointer_wrap
target/hexagon: Add guest reg reading functionality
target/hexagon/cpu.h | 11 +
target/hexagon/cpu_helper.h | 8 +
target/hexagon/gen_tcg.h | 7 -
target/hexagon/gen_tcg_sys.h | 27 +-
target/hexagon/helper.h | 3 +-
target/hexagon/hexswi.h | 17 ++
target/hexagon/idef-parser/parser-helpers.h | 2 +
target/hexagon/internal.h | 4 +
target/hexagon/macros.h | 3 -
target/hexagon/sys_macros.h | 7 +
target/hexagon/translate.h | 5 +-
target/hexagon/reg_fields_def.h.inc | 11 +
linux-user/hexagon/cpu_loop.c | 7 +
target/hexagon/cpu.c | 360 +++++++++++++++++++++-
target/hexagon/decode.c | 14 +
target/hexagon/genptr.c | 18 +-
target/hexagon/hex_mmu.c | 4 +-
target/hexagon/hexswi.c | 270 ++++++++++++++++
target/hexagon/idef-parser/parser-helpers.c | 9 +
target/hexagon/op_helper.c | 456 ++++++++++++++++++++++++++--
target/hexagon/translate.c | 216 ++++++++++++-
target/hexagon/hex_common.py | 3 +
target/hexagon/idef-parser/idef-parser.y | 3 +
target/hexagon/imported/encode_pp.def | 1 +
target/hexagon/imported/ldst.idef | 3 +
25 files changed, 1413 insertions(+), 56 deletions(-)
--
2.34.1
