On Mon, Jun 15, 2026 at 12:15 AM imaginos <[email protected]> wrote:
>
> The translator has supported mnret since commit 3157a553ec6b9a
> ("target/riscv: Add Smrnmi mnret instruction"), but the
> disassembler still renders it as illegal. Add it unguarded,
> since the encoding does not overlap any other extension.
>
> Signed-off-by: imaginos <[email protected]>
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> v2: rebase on riscv-to-apply.next
>
> disas/riscv.c | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/disas/riscv.c b/disas/riscv.c
> index b8ec546883..7f1b262773 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -989,6 +989,7 @@ typedef enum {
> rv_op_cbo_clean = 957,
> rv_op_cbo_flush = 958,
> rv_op_cbo_zero = 959,
> + rv_op_mnret = 960,
> } rv_op;
>
> /* register names */
> @@ -2263,6 +2264,7 @@ const rv_opcode_data rvi_opcode_data[] = {
> { "cbo.clean", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
> { "cbo.flush", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
> { "cbo.zero", rv_codec_r, rv_fmt_rs1, NULL, 0, 0, 0 },
> + { "mnret", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 },
> };
>
> /* CSR names */
> @@ -4077,6 +4079,11 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa
> isa)
> case 64: op = rv_op_mret; break;
> }
> break;
> + case 1792:
> + switch ((inst >> 15) & 0b1111111111) {
> + case 64: op = rv_op_mnret; break;
> + }
> + break;
> case 1952:
> switch ((inst >> 15) & 0b1111111111) {
> case 576: op = rv_op_dret; break;
> --
> 2.43.0
>
>
