On Thu, Jun 11, 2026 at 10:34 PM Daniel Henrique Barboza
<[email protected]> wrote:
>
> Next patch is going to dynamically allocate debug trigger arrays during
> realize() time.  We need a way of freeing them during unrealize(), which
> doesn't exist at this moment.
>
> There's a lot going on in that patch already so we're adding the
> callback infrastructure beforehand.
>
> Suggested-by: Philippe Mathieu-Daudé <[email protected]>
> Signed-off-by: Daniel Henrique Barboza <[email protected]>

Reviewed-by: Alistair Francis <[email protected]>

Alistair

> ---
>  target/riscv/cpu.c | 9 +++++++++
>  target/riscv/cpu.h | 2 ++
>  2 files changed, 11 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index c1b10cc7ef..5b2133d811 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -1012,6 +1012,13 @@ static void riscv_cpu_realize(DeviceState *dev, Error 
> **errp)
>      mcc->parent_realize(dev, errp);
>  }
>
> +static void riscv_cpu_unrealize(DeviceState *dev)
> +{
> +    RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
> +
> +    mcc->parent_unrealize(dev);
> +}
> +
>  bool riscv_cpu_accelerator_compatible(RISCVCPU *cpu)
>  {
>      if (tcg_enabled()) {
> @@ -2667,6 +2674,8 @@ static void riscv_cpu_common_class_init(ObjectClass *c, 
> const void *data)
>
>      device_class_set_parent_realize(dc, riscv_cpu_realize,
>                                      &mcc->parent_realize);
> +    device_class_set_parent_unrealize(dc, riscv_cpu_unrealize,
> +                                      &mcc->parent_unrealize);
>
>      resettable_class_set_parent_phases(rc, NULL, riscv_cpu_reset_hold, NULL,
>                                         &mcc->parent_phases);
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index c98652cd62..11cd710990 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -575,6 +575,7 @@ typedef struct RISCVCPUDef {
>  /**
>   * RISCVCPUClass:
>   * @parent_realize: The parent class' realize handler.
> + * @parent_unrealize: The parent class' unrealize handler.
>   * @parent_phases: The parent class' reset phase handlers.
>   *
>   * A RISCV CPU model.
> @@ -583,6 +584,7 @@ struct RISCVCPUClass {
>      CPUClass parent_class;
>
>      DeviceRealize parent_realize;
> +    DeviceUnrealize parent_unrealize;
>      ResettablePhases parent_phases;
>      RISCVCPUDef *def;
>  };
> --
> 2.43.0
>
>

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