From: Alistair Francis <[email protected]> The following changes since commit 2f28d34ea0aead9830478cd1d3d0dd9d9191d82e:
Merge tag 'pull-tcg-20260612' of https://gitlab.com/rth7680/qemu into staging (2026-06-13 14:02:34 -0400) are available in the Git repository at: https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20260616 for you to fetch changes up to e968e487acf082279118667f495a3f4275a59d59: hw/riscv: add create_fdt_socket_cpu_sifive() (2026-06-16 20:01:11 +1000) ---------------------------------------------------------------- RISC-V PR for 11.1 * Disable svpbmt if satp_mode is less then sv39 * Fix PMP address alignment * Mstatus write bug fixes * Add 'cbo' insns to disassembler * Do not hide Sstc CSRs from gdbstub * Reject Svinval instructions in U-mode * Save opcode before zicbo helpers * Fault with reserved PTE.PBMT val * Allow LOAD_ADDR_MIS promotion to AMO fault * Make riscv cpu.h target independent * Add PMA access fault * Disable svnapot if satp_mode is less then sv39 * Fix disassembler inst_length calculation * Add RISC-V big-endian target support * Add the implied rules for G and B extensions * Print privilege level and ELP in riscv_cpu_dump_state * Improve alignment in riscv_cpu_dump_state * Mask vxrm csrw write to the low 2 bits * Reorder Smrnmi CPU fields above CPU reset line * Supplement cpu topology arguments * Don't insert DDT cache in Bare mode * Fix 'iommu-map' FDT entry * Fix mstatus.FS dirty tracking for FP exception-raising instructions * Enable `mnret` disassembly * Add support for K230 board * FDT creation helpers ---------------------------------------------------------------- Abhigyan Kumar (1): target/riscv: mask vxrm csrw write to the low 2 bits Anton Blanchard (2): target/riscv: Print privilege level and ELP in riscv_cpu_dump_state target/riscv: Improve alignment in riscv_cpu_dump_state Anton Johansson (27): target/riscv: Fix size of gpr and gprh target/riscv: Fix size of vector CSRs target/riscv: Fix size of pc, load_[val|res] target/riscv: Fix size of frm and fflags target/riscv: Fix size of badaddr and bins target/riscv: Fix size of guest_phys_fault_addr target/riscv: Fix size of priv_ver and vext_ver target/riscv: Fix size of retxh target/riscv: Fix size of ssp target/riscv: Fix size of excp_uw2 target/riscv: Fix size of sw_check_code target/riscv: Fix size of priv target/riscv: Fix size of gei fields target/riscv: Fix size of [m|s|vs]iselect fields target/riscv: Fix arguments to board IMSIC emulation callbacks target/riscv: Fix size of irq_overflow_left target/riscv: Indent PMUFixedCtrState correctly target/riscv: Replace target_ulong in riscv_cpu_get_trap_name() target/riscv: Replace target_ulong in riscv_ctr_add_entry() target/riscv: Fix size of trigger data target/riscv: Fix size of mseccfg target/riscv: Move debug.h include away from cpu.h target/riscv: Move CSR declarations to separate csr.h header target/riscv: Introduce externally facing CSR access functions target/riscv: Make pmp.h target_ulong agnostic target/riscv: Pass address as uint64_t in cpu_set_exception_base() target/riscv: Fix pmp.h/cpu.h circular inclusion Chao Liu (5): target/riscv: add thead-c908 cpu support hw/riscv: add k230 board initial support hw/watchdog: add k230 watchdog initial support tests/qtest: add test for K230 watchdog docs/system/riscv: add documentation for k230 machine Daniel Henrique Barboza (24): target/riscv/tcg: disable svpbmt if satp_mode < sv39 target/riscv/csr.c: do not allow mstatus MPV/GVA writes target/riscv/csr.c: fix mstatus.UXL reserved value disas/riscv.c: add 'cbo' insns to disassembler target/riscv/insn_trans/trans_rvzicbo.c.inc: save opcode before helpers target/riscv/cpu_helper.c: fault with reserved PTE.PBMT val target/riscv/cpu_helper.c: allow LOAD_ADDR_MIS promotion to AMO fault target/riscv/cpu_helper.c: add PMA access fault target/riscv/tcg: disable svnapot if satp_mode < sv39 disas/riscv.c: fix inst_length() hw/riscv/virt.c: fix 'iommu-map' FDT entry hw/riscv/sifive_u.c: add a FDT phandle to cpu-intc hw/riscv: add fdt-common helper hw/riscv/numa: make numa_enabled() public hw/riscv: add create_fdt_socket_memory() helper hw/riscv/sifive_u.c: add intc_phandles array hw/riscv/spike.c: add intc_phandles array hw/riscv: add create_fdt_clint() helper hw/riscv/sifive_u.c: add cpu-map, cluster and core DTs hw/riscv: add fdt_create_cpu_socket_subnode() helper hw/riscv: add create_fdt_socket_cpus() hw/riscv/spike.c: use create_fdt_socket_cpus() hw/riscv/fdt_common.c: create create_fdt_socket_cpu_internal() hw/riscv: add create_fdt_socket_cpu_sifive() Djordje Todorovic (6): target/riscv: Implement runtime data endianness via MSTATUS bits target/riscv: Fix page table walk endianness for big-endian harts target/riscv: Add big-endian CPU configuration field and reset logic hw/riscv/boot: Honour data endianness target/riscv: Expose and document the CPU 'big-endian' property tests/functional: Add RISC-V endianness test Frank Chang (2): target/riscv: Add standard B extension implied rule target/riscv: Reorder Smrnmi CPU fields above CPU reset line Jay Chang (4): target/riscv: Align pmp size to pmp-granularity target/riscv: Improve PMP address alignment readability hw/riscv: Don't insert DDT cache in Bare mode hw/riscv: Refactor riscv_iommu_ctx_put() for Bare mode handling Jim Shu (1): target/riscv: Add the implied rule for G extension Max Chou (2): target/riscv: Set mstatus.FS dirty when scalar FP raises exceptions target/riscv: rvv: Set mstatus.FS dirty when vector FP raises exceptions Philippe Mathieu-Daudé (5): target/riscv: Initialize DisasContext::mo_endian once target/riscv: De-indent some code in get_physical_address() target/riscv: Remove target_ulong use in get_physical_address() hw/riscv/boot: Rewrite setup_rom_reset_vec() using load/store API hw/riscv/boot: Replace cpu_to_le32() -> const_le32() Xuemei Liu (1): hw/riscv/numa.c: Supplement cpu topology arguments Zephyr Li (2): target/riscv: Do not hide Sstc CSRs from gdbstub target/riscv: Reject Svinval instructions in U-mode imaginos (1): disas/riscv: enable `mnret` disassembly MAINTAINERS | 11 + docs/system/riscv/k230.rst | 113 ++++++ docs/system/target-riscv.rst | 30 ++ include/hw/riscv/fdt-common.h | 33 ++ include/hw/riscv/k230.h | 149 +++++++ include/hw/riscv/numa.h | 8 + include/hw/watchdog/k230_wdt.h | 121 ++++++ target/riscv/cpu-qom.h | 2 + target/riscv/cpu.h | 287 +++++--------- target/riscv/csr.h | 102 +++++ target/riscv/debug.h | 2 - target/riscv/internals.h | 33 +- target/riscv/pmp.h | 23 +- target/riscv/pmu.h | 2 +- target/riscv/cpu_cfg_fields.h.inc | 1 + target/riscv/insn32.decode | 2 +- disas/riscv.c | 56 ++- hw/intc/riscv_imsic.c | 34 +- hw/riscv/boot.c | 95 ++--- hw/riscv/fdt-common.c | 202 ++++++++++ hw/riscv/k230.c | 526 +++++++++++++++++++++++++ hw/riscv/numa.c | 32 +- hw/riscv/riscv-iommu.c | 34 +- hw/riscv/riscv_hart.c | 7 +- hw/riscv/sifive_u.c | 88 +---- hw/riscv/spike.c | 123 ++---- hw/riscv/virt.c | 185 ++------- hw/watchdog/k230_wdt.c | 296 ++++++++++++++ linux-user/riscv/signal.c | 5 +- target/riscv/cpu.c | 140 ++++++- target/riscv/cpu_helper.c | 180 ++++++--- target/riscv/csr.c | 116 ++++-- target/riscv/debug.c | 1 + target/riscv/fpu_helper.c | 167 ++++++-- target/riscv/gdbstub.c | 3 +- target/riscv/kvm/kvm-cpu.c | 1 + target/riscv/machine.c | 81 ++-- target/riscv/mips_csr.c | 1 + target/riscv/monitor.c | 3 +- target/riscv/op_helper.c | 28 +- target/riscv/pmp.c | 34 +- target/riscv/pmu.c | 9 +- target/riscv/riscv-qmp-cmds.c | 1 + target/riscv/tcg/tcg-cpu.c | 63 ++- target/riscv/th_csr.c | 377 +++++++++++++++++- target/riscv/translate.c | 82 ++-- target/riscv/vector_helper.c | 366 +++++++++-------- tests/qtest/k230-wdt-test.c | 189 +++++++++ target/riscv/insn_trans/trans_privileged.c.inc | 2 +- target/riscv/insn_trans/trans_rva.c.inc | 4 +- target/riscv/insn_trans/trans_rvd.c.inc | 4 +- target/riscv/insn_trans/trans_rvf.c.inc | 4 +- target/riscv/insn_trans/trans_rvi.c.inc | 24 +- target/riscv/insn_trans/trans_rvm.c.inc | 16 +- target/riscv/insn_trans/trans_rvv.c.inc | 22 +- target/riscv/insn_trans/trans_rvzacas.c.inc | 4 +- target/riscv/insn_trans/trans_rvzalasr.c.inc | 4 +- target/riscv/insn_trans/trans_rvzce.c.inc | 4 +- target/riscv/insn_trans/trans_rvzfh.c.inc | 4 +- target/riscv/insn_trans/trans_rvzicbo.c.inc | 8 + target/riscv/insn_trans/trans_rvzicfiss.c.inc | 26 +- target/riscv/insn_trans/trans_svinval.c.inc | 12 + target/riscv/insn_trans/trans_xmips.c.inc | 8 +- target/riscv/insn_trans/trans_xthead.c.inc | 16 +- target/riscv/insn_trans/trans_zilsd.c.inc | 4 +- hw/riscv/Kconfig | 11 + hw/riscv/meson.build | 3 +- hw/watchdog/Kconfig | 4 + hw/watchdog/meson.build | 1 + hw/watchdog/trace-events | 9 + tests/functional/riscv64/meson.build | 1 + tests/functional/riscv64/test_endianness.py | 57 +++ tests/qtest/meson.build | 3 +- 73 files changed, 3544 insertions(+), 1155 deletions(-) create mode 100644 docs/system/riscv/k230.rst create mode 100644 include/hw/riscv/fdt-common.h create mode 100644 include/hw/riscv/k230.h create mode 100644 include/hw/watchdog/k230_wdt.h create mode 100644 target/riscv/csr.h create mode 100644 hw/riscv/fdt-common.c create mode 100644 hw/riscv/k230.c create mode 100644 hw/watchdog/k230_wdt.c create mode 100644 tests/qtest/k230-wdt-test.c create mode 100644 tests/functional/riscv64/test_endianness.py
