On Tue, 2 Jun 2026 at 07:34, Kuan-Jui Chiu <[email protected]> wrote: > > This patch adds new model for Axiado SoC AX3000 which supports > 4 Cortex-A53 ARM64 CPUs > Arm Generic Interrupt Controller v3 > 4 Cadence UARTs > > Signed-off-by: Kuan-Jui Chiu <[email protected]> > --- > MAINTAINERS | 7 ++ > hw/arm/Kconfig | 7 ++ > hw/arm/ax3000-soc.c | 218 ++++++++++++++++++++++++++++++++++++ > hw/arm/meson.build | 3 + > include/hw/arm/ax3000-soc.h | 71 ++++++++++++ > 5 files changed, 306 insertions(+) > create mode 100644 hw/arm/ax3000-soc.c > create mode 100644 include/hw/arm/ax3000-soc.h > > diff --git a/MAINTAINERS b/MAINTAINERS > index cd5c4831e27..3782c83738a 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -1298,6 +1298,13 @@ M: Manos Pitsidianakis <[email protected]> > S: Maintained > F: rust/hw/char/pl011/ > > +Axiado SoCs and EVKs > +M: Kuan-Jui Chiu <[email protected]> > +L: [email protected] > +S: Maintained > +F: hw/arm/ax3000*.c > +F: include/hw/arm/ax3000*.h > + > AVR Machines > ------------- > > diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig > index 5b198402d5e..39f0b652a0f 100644 > --- a/hw/arm/Kconfig > +++ b/hw/arm/Kconfig > @@ -716,3 +716,10 @@ config ARMSSE > select UNIMP > select SSE_COUNTER > select SSE_TIMER > + > +config AXIADO_SOC > + bool > + depends on ARM > + select ARM_GIC > + select CADENCE # UART > + select UNIMP > diff --git a/hw/arm/ax3000-soc.c b/hw/arm/ax3000-soc.c > new file mode 100644 > index 00000000000..517cc6f52d5 > --- /dev/null > +++ b/hw/arm/ax3000-soc.c > @@ -0,0 +1,218 @@ > +/* > + * Axiado SoC AX3000 > + * > + * Author: Kuan-Jui Chiu <[email protected]> > + * > + * SPDX-License-Identifier: GPL-2.0-or-later > + */ > + > +#include "qemu/osdep.h" > +#include "system/address-spaces.h" > +#include "hw/arm/bsa.h" > +#include "hw/arm/ax3000-soc.h" > +#include "hw/misc/unimp.h" > +#include "system/system.h" > +#include "qobject/qlist.h" > +#include "qom/object.h" > +#include "hw/core/boards.h" > + > +static uint64_t pll_read(void *opaque, hwaddr offset, unsigned size) > +{ > + switch (offset) { > + case CLKRST_CPU_PLL_POSTDIV_OFFSET: > + return 0x20891b; > + case CLKRST_CPU_PLL_STS_OFFSET: > + return 0x01; > + default: > + return 0x00; > + } > +} > + > +static void pll_write(void *opaque, hwaddr offset, uint64_t val, unsigned > size) > +{ > +} > + > +static const MemoryRegionOps pll_ops = { > + .read = pll_read, > + .write = pll_write, > + .endianness = DEVICE_LITTLE_ENDIAN, > + .impl = { > + .min_access_size = 4, > + .max_access_size = 4, > + }, > + .valid = { > + .min_access_size = 4, > + .max_access_size = 4, > + } > +};
This needs to be its own device model. Don't set up and map a MemoryRegionOps directly in this SoC object. thanks -- PMM
