This helper decode the ID reg writable mask, matches it against ID reg fields defined in target/arm/cpu-idregs.h.inc and for each writable named field, generates a uint64 property.
REVIDR_EL1 and AIDR_EL1 are writable but they do not expose any field. They will be handled separately. Signed-off-by: Eric Auger <[email protected]> --- v5 -> v6 - for enum values, check against value value when setting the prop - do not check writable_map flag anymore v4 -> v5: - free prop_name - check cpu->writable_map as a preamble in kvm_arm_expose_idreg_properties --- target/arm/kvm_arm.h | 10 +++ target/arm/kvm.c | 144 ++++++++++++++++++++++++++++++++++++++++ target/arm/trace-events | 4 ++ 3 files changed, 158 insertions(+) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index e7c40fb003..2b3474cc36 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -142,6 +142,16 @@ void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu); */ void kvm_arm_add_vcpu_properties(ARMCPU *cpu); +typedef struct ARM64SysReg ARM64SysReg; +/** + * kvm_arm_expose_idreg_properties: + * @cpu: The CPU object to generate the properties for + * @reg: registers from the host + * + * analyze the writable mask and generate properties for writable fields + */ +void kvm_arm_expose_idreg_properties(ARMCPU *cpu, ARM64SysReg *regs); + /** * kvm_arm_steal_time_finalize: * @cpu: ARMCPU for which to finalize kvm-steal-time diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 71a214f228..54392f3077 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -327,6 +327,150 @@ static int get_host_cpu_idregs(ARMCPU *cpu, int fd, ARMHostCPUFeatures *ahcf) return err; } +static ARM64SysRegField *get_field(int i, ARM64SysReg *reg) +{ + for (int f = 0; f < reg->fields_count; f++) { + struct ARM64SysRegField *field = ®->fields[f]; + int upper = field->shift + field->length - 1; + + if (i >= field->shift && i <= upper) { + return field; + } + } + return NULL; +} + +static void set_sysreg_prop(Object *obj, Visitor *v, + const char *name, void *opaque, + Error **errp) +{ + ARM64SysRegField *field = (ARM64SysRegField *)opaque; + ARMCPU *cpu = ARM_CPU(obj); + uint64_t *idregs = cpu->isar.idregs; + uint64_t old, value, mask; + int lower = field->shift; + int length = field->length; + int index = field->index; + + if (!visit_type_uint64(v, name, &value, errp)) { + return; + } + + if (length < 64 && value > ((1 << length) - 1)) { + error_setg(errp, + "idreg %s set value (0x%lx) exceeds length of field (%d)!", + name, value, length); + return; + } + + if (field->arch_vals) { + /* this field has some enum values */ + for (int i = 0; i < field->arch_vals_count; i++) { + if (value == field->arch_vals[i].value) { + goto valid; + } + } + error_setg(errp, + "idreg %s set value (0x%lx) does not match any " + "arch valid enum value!", name, value); + return; + } + +valid: + + mask = MAKE_64BIT_MASK(lower, length); + value = value << lower; + old = idregs[index]; + idregs[index] = old & ~mask; + idregs[index] |= value; + trace_set_sysreg_prop(name, old, mask, value, idregs[index]); +} + +static void get_sysreg_prop(Object *obj, Visitor *v, + const char *name, void *opaque, + Error **errp) +{ + ARM64SysRegField *field = (ARM64SysRegField *)opaque; + ARMCPU *cpu = ARM_CPU(obj); + uint64_t *idregs = cpu->isar.idregs; + uint64_t value, mask; + int lower = field->shift; + int length = field->length; + int index = field->index; + + mask = MAKE_64BIT_MASK(lower, length); + value = (idregs[index] & mask) >> lower; + visit_type_uint64(v, name, &value, errp); + trace_get_sysreg_prop(name, value); +} + +/* + * decode_idreg_writemap: Generate props for writable fields + * + * @obj: CPU object + * @reg: description of the sysreg + */ +static int +decode_idreg_writemap(Object *obj, ARM64SysReg *reg) +{ + uint64_t map = reg->writable_mask; + int i = ctz64(map); + int nb_sysreg_props = 0; + + while (map) { + ARM64SysRegField *field = get_field(i, reg); + int lower, upper; + char *prop_name; + uint64_t field_mask; + + if (!field) { + warn_report("%s bit %d of %s is writable but no named field " + "in target/arm/cpu-idregs.h.inc", + __func__, i, reg->name); + warn_report("%s is target/arm/cpu-idregs.h.inc up-to-date?", __func__); + map = map & ~BIT_ULL(i); + i = ctz64(map); + continue; + } + lower = field->shift; + upper = field->shift + field->length - 1; + prop_name = g_strdup_printf("SYSREG_%s_%s", reg->name, field->name); + trace_decode_idreg_writemap(field->name, lower, upper, prop_name); + object_property_add(obj, prop_name, "uint64", + get_sysreg_prop, set_sysreg_prop, NULL, field); + g_free(prop_name); + nb_sysreg_props++; + + field_mask = MAKE_64BIT_MASK(lower, field->length); + map = map & ~field_mask; + i = ctz64(map); + } + trace_nb_sysreg_props(reg->name, nb_sysreg_props); + return 0; +} + +/* analyze the writable mask and generate properties for writable fields */ +void kvm_arm_expose_idreg_properties(ARMCPU *cpu, ARM64SysReg *regs) +{ + Object *obj = OBJECT(cpu); + + for (int i = 0; i < NUM_ID_IDX; i++) { + ARM64SysReg *sysregdesc = ®s[i]; + + if (sysregdesc->writable_mask) { + /* + * special case REVIDR_EL1 and AIDR_EL1 which are writable but + * do not expose named fields. They will need to be handled + * separately + */ + if (strcmp(sysregdesc->name, "REVIDR_EL1") && + strcmp(sysregdesc->name, "AIDR_EL1")) { + decode_idreg_writemap(obj, sysregdesc); + } + } + } +} + static void kvm_arm_get_host_cpu_features(ARMCPU *cpu, ARMHostCPUFeatures *ahcf) { diff --git a/target/arm/trace-events b/target/arm/trace-events index c25d2a1191..d72ad6b671 100644 --- a/target/arm/trace-events +++ b/target/arm/trace-events @@ -15,6 +15,10 @@ arm_gt_update_irq(int timer, int irqstate) "gt_update_irq: timer %d irqstate %d" kvm_arm_fixup_msi_route(uint64_t iova, uint64_t gpa) "MSI iova = 0x%"PRIx64" is translated into 0x%"PRIx64 get_host_cpu_idregs(const char *name, uint64_t value) "scratch vcpu host value for %s is 0x%"PRIx64 kvm_arm_writable_idregs_to_cpreg_list(const char *name, uint64_t previous, uint64_t new) "%s overwrite default 0x%"PRIx64" with 0x%"PRIx64 +decode_idreg_writemap(const char* name, int lower, int upper, char *prop_name) "%s [%d:%d] is writable (prop %s)" +get_sysreg_prop(const char *name, uint64_t value) "%s 0x%"PRIx64 +set_sysreg_prop(const char *name, uint64_t old, uint64_t mask, uint64_t field_value, uint64_t new) "%s old reg value=0x%"PRIx64" mask=0x%"PRIx64" new field value=0x%"PRIx64" new reg value=0x%"PRIx64 +nb_sysreg_props(const char *name, int count) "%s: %d SYSREG properties" # cpu.c arm_cpu_reset(uint64_t mp_aff) "cpu %" PRIu64 -- 2.53.0
