Armv8-M Protected Memory System Architecture can only be emulated, therefore restrict it to TCG to avoid compiling it on hardware accelerators.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]> --- target/arm/ptw.c | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 8b54018c988..1470de30108 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -13,11 +13,13 @@ #include "exec/page-protection.h" #include "exec/target_page.h" #include "exec/tlb-flags.h" +#ifdef CONFIG_TCG #include "accel/tcg/probe.h" +#include "target/arm/tcg/idau.h" +#endif #include "cpu.h" #include "internals.h" #include "cpu-features.h" -#include "target/arm/tcg/idau.h" typedef struct S1Translate { /* @@ -2818,6 +2820,8 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, return (ptw->in_prot_check & ~result->f.prot) == 0; } +#ifdef CONFIG_TCG + static uint32_t *regime_rbar(CPUARMState *env, ARMMMUIdx mmu_idx, uint32_t secure) { @@ -3247,6 +3251,20 @@ static bool get_phys_addr_pmsav8(CPUARMState *env, return ret; } +#else /* !CONFIG_TCG */ + +static bool get_phys_addr_pmsav8(CPUARMState *env, + S1Translate *ptw, + uint32_t address, + MMUAccessType access_type, + GetPhysAddrResult *result, + ARMMMUFaultInfo *fi) +{ + g_assert_not_reached(); +} + +#endif /* !CONFIG_TCG */ + /* * Translate from the 4-bit stage 2 representation of * memory attributes (without cache-allocation hints) to -- 2.53.0
