On 13.03.2026 19:47, Thierry Escande wrote:
From: Alexey Gerasimenko <[email protected]>
There are two small issues in PCIEXBAR address mask handling:
- wrong bit positions for address mask bits (see PCIEXBAR description
in Q35 datasheet)
- incorrect usage of 64ADR_MASK
Due to this, attempting to write a valid PCIEXBAR address may cause it
to shift to another address, causing memory layout corruption where
emulated MMIO regions may overlap real (passed through) MMIO ranges. Fix
this by providing correct values.
I'm not sure about the implication of this issue, - is it qemu-stable
material?
Thanks,
/mjt
