Hi Zephyr,
Sorry to take this long to take a look at this work. I did it last Thursday.
The overall idea is correct: we need to remove TCG exclusive bits out of the
way of the KVM build. Our current code layout is awful for it though, and
this is the root cause that needs addressing.
We have too much stuff at the target/riscv dir which is supposed to be code
that is accel agnostic, and unfortunately this led you to wrong conclusions.
For example, in patch 1, where you're moving validation code to from tcg-cpu.c
a cpu-validate.c common file. KVM doesn't care about any of that - KVM
validation is done at init time by the kernel module. It doesn't care about
riscv_cpu_validate_set_extensions() and any of that.
For the record we had a series in 2023 that tried to fix --disable-tcg:
https://lore.kernel.org/qemu-devel/[email protected]/
but at that time we had other stuff going in parallel and the series eventually
stopped applying and that was that. Which is a shame because that series was
closer to what we need, but I won't ask Phil to re-send that again because it's
a rather unpleasant rebase.
Unfortunately I don't see a sane way forward aside from doing the grunt and
gruesome work first, i.e. putting TCG specific files in the TCG dir, like x86
and loongarch is doing, then go through each problem that --disable-tcg points
out, fix it, and do that over and over until we have a working build. And
there's a high chance that we might break some unintended stuff in the KVM
driver regardless.
I'll send such a series later today. I ended up using 2 patches from your
series (patch 1 from v2 and patch 6 from v3). Hopefully we'll be able to
put this --disable-tcg business to rest.
Thanks,
Daniel
On 6/2/2026 6:17 AM, Zephyr Li wrote:
This series fixes the riscv64-softmmu --disable-tcg build by keeping
TCG-only code out of no-TCG builds while preserving common RISC-V CPU
helpers for non-TCG configurations.
Compared with v2, this version replaces the no-TCG stub for
riscv_cpu_validate_set_extensions() with a common cpu-validate.c split.
The validator is used by common CSR code and should not live in TCG-only
code.
Changes in v3:
- Replace the no-TCG stub with a new cpu-validate.c common source file.
- Move common RISC-V extension validation and user-option tracking out of
target/riscv/tcg/tcg-cpu.c.
- Move fflags and exception helpers out of TCG-only helper files.
- Reject x-misa-w outside TCG.
- Build RISC-V TCG-only sources only when CONFIG_TCG is enabled.
- Add GitLab CI coverage for riscv64 KVM-only --disable-tcg builds.
Testing:
- ../configure --target-list=riscv64-softmmu --enable-kvm --disable-tcg \
--enable-debug
ninja
- ../configure --target-list=riscv64-softmmu,riscv64-linux-user \
--enable-debug
ninja
- In the no-TCG build:
qemu-system-riscv64 -M virt,accel=qtest -cpu rv64,x-misa-w=true \
-nographic -S
reports "x-misa-w requires TCG".
- In the TCG build:
qemu-system-riscv64 -M virt -accel tcg -cpu rv64,x-misa-w=true \
-nographic -S
starts without reporting "x-misa-w requires TCG".
Zephyr Li (6):
target/riscv: move extension validation out of TCG-only code
target/riscv: move fflags helpers to common code
target/riscv: move riscv_raise_exception() out of op_helper.c
target/riscv: reject x-misa-w outside TCG
target/riscv: build TCG-only sources only with TCG
gitlab-ci.d/crossbuilds: add riscv64 KVM-only build job
.gitlab-ci.d/crossbuilds.yml | 8 +
target/riscv/cpu-validate.c | 630 ++++++++++++++++++++++++++++++++++
target/riscv/cpu.c | 13 +-
target/riscv/cpu.h | 7 -
target/riscv/cpu_helper.c | 53 +++
target/riscv/csr.c | 12 +-
target/riscv/debug.c | 1 +
target/riscv/fpu_helper.c | 27 --
target/riscv/internals.h | 26 ++
target/riscv/meson.build | 10 +-
target/riscv/op_helper.c | 15 -
target/riscv/tcg/tcg-cpu.c | 637 ++---------------------------------
target/riscv/tcg/tcg-cpu.h | 1 -
target/riscv/zce_helper.c | 1 +
14 files changed, 769 insertions(+), 672 deletions(-)
create mode 100644 target/riscv/cpu-validate.c
base-commit: 5611a9268dae7b7ff99d478ed134052a9fc7e9f7
