On 22/6/26 21:31, Daniel Henrique Barboza wrote:
We have *way* too much TCG-only code hanging around in target/riscv,
where ideally we would have things that are shared between accelerators.
We'll follow the example of other targets like i386 and loongarch and
move everything to the tcg subir. This will not only cleanup target/riscv
but it will also expose what is common code but it's buried inside a TCG
helper.
We're leaving some stuff behind because these require a little more
case to not end up breaking KVM. We'll take care of them next.
Signed-off-by: Daniel Henrique Barboza <[email protected]>
---
target/riscv/meson.build | 16 ----------
target/riscv/{ => tcg}/bitmanip_helper.c | 0
target/riscv/{ => tcg}/cpu_helper.c | 0
target/riscv/{ => tcg}/crypto_helper.c | 0
target/riscv/{ => tcg}/csr.c | 0
target/riscv/{ => tcg}/debug.c | 0
target/riscv/{ => tcg}/fpu_helper.c | 0
.../insn_trans/trans_privileged.c.inc | 0
.../{ => tcg}/insn_trans/trans_rva.c.inc | 0
.../{ => tcg}/insn_trans/trans_rvb.c.inc | 0
.../{ => tcg}/insn_trans/trans_rvbf16.c.inc | 0
.../{ => tcg}/insn_trans/trans_rvd.c.inc | 0
.../{ => tcg}/insn_trans/trans_rvf.c.inc | 0
.../{ => tcg}/insn_trans/trans_rvh.c.inc | 0
.../{ => tcg}/insn_trans/trans_rvi.c.inc | 0
.../{ => tcg}/insn_trans/trans_rvk.c.inc | 0
.../{ => tcg}/insn_trans/trans_rvm.c.inc | 0
.../{ => tcg}/insn_trans/trans_rvv.c.inc | 0
.../{ => tcg}/insn_trans/trans_rvvk.c.inc | 0
.../{ => tcg}/insn_trans/trans_rvzabha.c.inc | 0
.../{ => tcg}/insn_trans/trans_rvzacas.c.inc | 0
.../{ => tcg}/insn_trans/trans_rvzalasr.c.inc | 0
.../{ => tcg}/insn_trans/trans_rvzawrs.c.inc | 0
.../{ => tcg}/insn_trans/trans_rvzce.c.inc | 0
.../{ => tcg}/insn_trans/trans_rvzcmop.c.inc | 0
.../{ => tcg}/insn_trans/trans_rvzfa.c.inc | 0
.../{ => tcg}/insn_trans/trans_rvzfh.c.inc | 0
.../{ => tcg}/insn_trans/trans_rvzicbo.c.inc | 0
.../insn_trans/trans_rvzicfiss.c.inc | 0
.../{ => tcg}/insn_trans/trans_rvzicond.c.inc | 0
.../{ => tcg}/insn_trans/trans_rvzimop.c.inc | 0
.../{ => tcg}/insn_trans/trans_svinval.c.inc | 0
.../{ => tcg}/insn_trans/trans_xlrbr.c.inc | 0
.../{ => tcg}/insn_trans/trans_xmips.c.inc | 0
.../{ => tcg}/insn_trans/trans_xthead.c.inc | 0
.../insn_trans/trans_xventanacondops.c.inc | 0
.../{ => tcg}/insn_trans/trans_zilsd.c.inc | 0
target/riscv/{ => tcg}/m128_helper.c | 0
target/riscv/tcg/meson.build | 30 +++++++++++++++++--
target/riscv/{ => tcg}/mips_csr.c | 0
target/riscv/{ => tcg}/op_helper.c | 0
target/riscv/{ => tcg}/pmu.c | 0
target/riscv/{ => tcg}/th_csr.c | 0
target/riscv/{ => tcg}/translate.c | 0
target/riscv/{ => tcg}/vcrypto_helper.c | 0
target/riscv/{ => tcg}/vector_helper.c | 0
target/riscv/{ => tcg}/vector_internals.c | 0
target/riscv/{ => tcg}/vector_internals.h | 0
target/riscv/{ => tcg}/zce_helper.c | 0
49 files changed, 28 insertions(+), 18 deletions(-)
rename target/riscv/{ => tcg}/bitmanip_helper.c (100%)
rename target/riscv/{ => tcg}/cpu_helper.c (100%)
rename target/riscv/{ => tcg}/crypto_helper.c (100%)
rename target/riscv/{ => tcg}/csr.c (100%)
rename target/riscv/{ => tcg}/debug.c (100%)
rename target/riscv/{ => tcg}/fpu_helper.c (100%)
rename target/riscv/{ => tcg}/insn_trans/trans_privileged.c.inc (100%)
rename target/riscv/{ => tcg}/insn_trans/trans_rva.c.inc (100%)
rename target/riscv/{ => tcg}/insn_trans/trans_rvb.c.inc (100%)
rename target/riscv/{ => tcg}/insn_trans/trans_rvbf16.c.inc (100%)
rename target/riscv/{ => tcg}/insn_trans/trans_rvd.c.inc (100%)
rename target/riscv/{ => tcg}/insn_trans/trans_rvf.c.inc (100%)
rename target/riscv/{ => tcg}/insn_trans/trans_rvh.c.inc (100%)
rename target/riscv/{ => tcg}/insn_trans/trans_rvi.c.inc (100%)
rename target/riscv/{ => tcg}/insn_trans/trans_rvk.c.inc (100%)
rename target/riscv/{ => tcg}/insn_trans/trans_rvm.c.inc (100%)
rename target/riscv/{ => tcg}/insn_trans/trans_rvv.c.inc (100%)
rename target/riscv/{ => tcg}/insn_trans/trans_rvvk.c.inc (100%)
rename target/riscv/{ => tcg}/insn_trans/trans_rvzabha.c.inc (100%)
rename target/riscv/{ => tcg}/insn_trans/trans_rvzacas.c.inc (100%)
rename target/riscv/{ => tcg}/insn_trans/trans_rvzalasr.c.inc (100%)
rename target/riscv/{ => tcg}/insn_trans/trans_rvzawrs.c.inc (100%)
rename target/riscv/{ => tcg}/insn_trans/trans_rvzce.c.inc (100%)
rename target/riscv/{ => tcg}/insn_trans/trans_rvzcmop.c.inc (100%)
rename target/riscv/{ => tcg}/insn_trans/trans_rvzfa.c.inc (100%)
rename target/riscv/{ => tcg}/insn_trans/trans_rvzfh.c.inc (100%)
rename target/riscv/{ => tcg}/insn_trans/trans_rvzicbo.c.inc (100%)
rename target/riscv/{ => tcg}/insn_trans/trans_rvzicfiss.c.inc (100%)
rename target/riscv/{ => tcg}/insn_trans/trans_rvzicond.c.inc (100%)
rename target/riscv/{ => tcg}/insn_trans/trans_rvzimop.c.inc (100%)
rename target/riscv/{ => tcg}/insn_trans/trans_svinval.c.inc (100%)
rename target/riscv/{ => tcg}/insn_trans/trans_xlrbr.c.inc (100%)
rename target/riscv/{ => tcg}/insn_trans/trans_xmips.c.inc (100%)
rename target/riscv/{ => tcg}/insn_trans/trans_xthead.c.inc (100%)
rename target/riscv/{ => tcg}/insn_trans/trans_xventanacondops.c.inc (100%)
rename target/riscv/{ => tcg}/insn_trans/trans_zilsd.c.inc (100%)
rename target/riscv/{ => tcg}/m128_helper.c (100%)
rename target/riscv/{ => tcg}/mips_csr.c (100%)
rename target/riscv/{ => tcg}/op_helper.c (100%)
rename target/riscv/{ => tcg}/pmu.c (100%)
rename target/riscv/{ => tcg}/th_csr.c (100%)
rename target/riscv/{ => tcg}/translate.c (100%)
rename target/riscv/{ => tcg}/vcrypto_helper.c (100%)
rename target/riscv/{ => tcg}/vector_helper.c (100%)
rename target/riscv/{ => tcg}/vector_internals.c (100%)
rename target/riscv/{ => tcg}/vector_internals.h (100%)
rename target/riscv/{ => tcg}/zce_helper.c (100%)
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
