On Tue, 23 Jun 2026 at 01:58, Alejandro Jimenez <[email protected]> wrote: > > When IOMMU x2APIC interrupts generation (IntCapXTEn) is enabled, > amdvi_build_xt_msi_msg() builds an MSI message using the relevant values in > the XT IOMMU General Interrupt Control Register. > > Initialize the local X86IOMMUIrq structure with zero for all fields. This > ensures that X86IOMMUIrq fields not set in the XT register (e.g. > msi_addr_last_bits) are initialized before x86_iommu_irq_to_msi_message() > consumes them. > > Remove the redundant 'struct' keyword in X86IOMMUIrq irq declaration. > > CID: 1660056 > Fixes: cf0210df65aa ("amd_iommu: Generate XT interrupts when xt support is > enabled") > Reported-by: Peter Maydell <[email protected]> > Suggested-by: Peter Maydell <[email protected]> > Signed-off-by: Alejandro Jimenez <[email protected]> > --- > hw/i386/amd_iommu.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c > index 0d273fd33d..9005dc7aab 100644 > --- a/hw/i386/amd_iommu.c > +++ b/hw/i386/amd_iommu.c > @@ -195,7 +195,7 @@ static void amdvi_assign_andq(AMDVIState *s, hwaddr addr, > uint64_t val) > static void amdvi_build_xt_msi_msg(AMDVIState *s, MSIMessage *msg) > { > union mmio_xt_intr xt_reg; > - struct X86IOMMUIrq irq; > + X86IOMMUIrq irq = { 0 };
This is fine for the Coverity problem, but you do also need to get rid of the bitfield-union as a separate issue. Reviewed-by: Peter Maydell <[email protected]> thanks -- PMM
