From: Abhigyan Kumar <[email protected]> RISC-V Privileged Specification 3.1.8 (Machine Trap Delegation Registers (medeleg and mideleg)) mentions:
"For exceptions that cannot occur in less privileged modes, the corresponding medeleg bits should be read-only zero. In particular, medeleg[11] is read-only zero." QEMU incorrectly included RISCV_EXCP_M_ECALL in DELEGABLE_EXCPS. It allowed the 11th bit to be written and read as set. Fixed by removing it from the DELEGABLE_EXCPS mask, adhering to the specification. Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3438 Signed-off-by: Abhigyan Kumar <[email protected]> Reviewed-by: Alistair Francis <[email protected]> Message-ID: <[email protected]> [ Changes by AF: - Remove comment ] Signed-off-by: Alistair Francis <[email protected]> (cherry picked from commit a0946caf1d9ec21446ebdcb5eab2400baa4323ae) Signed-off-by: Michael Tokarev <[email protected]> diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 51e668b46d..35e98df420 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1789,7 +1789,6 @@ static const uint64_t all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS | (1ULL << (RISCV_EXCP_U_ECALL)) | \ (1ULL << (RISCV_EXCP_S_ECALL)) | \ (1ULL << (RISCV_EXCP_VS_ECALL)) | \ - (1ULL << (RISCV_EXCP_M_ECALL)) | \ (1ULL << (RISCV_EXCP_INST_PAGE_FAULT)) | \ (1ULL << (RISCV_EXCP_LOAD_PAGE_FAULT)) | \ (1ULL << (RISCV_EXCP_STORE_PAGE_FAULT)) | \ -- 2.47.3
