On 24/6/26 21:59, Alejandro Jimenez wrote:
The XT IOMMU General Interrupt Control Register is a guest-visible MMIO register. Decoding it with bitfields depends on host bitfield layout and is not portable to big-endian hosts.Fix this by removing union mmio_xt_intr and explicitly extracting fields with FIELD_EX64() from the full register value returned by amdvi_readq(), which has already been converted to host endianness. Using a designated initializer for X86IOMMUIrq also ensures fields not provided by the XT register (e.g. msi_addr_last_bits) are initialized before x86_iommu_irq_to_msi_message() uses them. CID: 1660056 Fixes: cf0210df65aa ("amd_iommu: Generate XT interrupts when xt support is enabled") Reported-by: Peter Maydell <[email protected]> Suggested-by: Peter Maydell <[email protected]> Signed-off-by: Alejandro Jimenez <[email protected]> --- hw/i386/amd_iommu.c | 28 ++++++++++++++++++---------- hw/i386/amd_iommu.h | 14 -------------- 2 files changed, 18 insertions(+), 24 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
