Replace the deprecated device_class_set_legacy_reset() registration with the three-phase resettable interface, following the pattern already established by the CXL root port (cxl_rp_reset_hold).
Only the hold phase is needed; enter and exit are left NULL. The parent hold phase is chained for correctness: TYPE_PCI_DEVICE installs no hold phase today, so parent_phases.hold is currently NULL and the chained call is a no-op, but capturing and invoking it is the correct forward-compatible pattern and mirrors cxl_rp_reset_hold(). No functional change — the reset body is identical; only the registration path and function signature change. Signed-off-by: Junjie Cao <[email protected]> --- hw/mem/cxl_type3.c | 16 ++++++++++++---- include/hw/cxl/cxl_device.h | 2 ++ 2 files changed, 14 insertions(+), 4 deletions(-) diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c index 4ac6eaa950..b842e71c66 100644 --- a/hw/mem/cxl_type3.c +++ b/hw/mem/cxl_type3.c @@ -1326,13 +1326,18 @@ MemTxResult cxl_type3_write(PCIDevice *d, hwaddr host_addr, uint64_t data, return address_space_write(as, dpa_offset, attrs, &data, size); } -static void ct3d_reset(DeviceState *dev) +static void ct3d_reset_hold(Object *obj, ResetType type) { - CXLType3Dev *ct3d = CXL_TYPE3(dev); + CXLType3Dev *ct3d = CXL_TYPE3(obj); + CXLType3Class *cvc = CXL_TYPE3_GET_CLASS(obj); uint32_t *reg_state = ct3d->cxl_cstate.crb.cache_mem_registers; uint32_t *write_msk = ct3d->cxl_cstate.crb.cache_mem_regs_write_mask; - pcie_cap_fill_link_ep_usp(PCI_DEVICE(dev), ct3d->width, ct3d->speed, + if (cvc->parent_phases.hold) { + cvc->parent_phases.hold(obj, type); + } + + pcie_cap_fill_link_ep_usp(PCI_DEVICE(obj), ct3d->width, ct3d->speed, ct3d->flitmode); cxl_component_register_init_common(reg_state, write_msk, CXL2_TYPE3_DEVICE, ct3d->hdmdb); @@ -2464,6 +2469,7 @@ static void ct3_class_init(ObjectClass *oc, const void *data) DeviceClass *dc = DEVICE_CLASS(oc); PCIDeviceClass *pc = PCI_DEVICE_CLASS(oc); CXLType3Class *cvc = CXL_TYPE3_CLASS(oc); + ResettableClass *rc = RESETTABLE_CLASS(oc); pc->realize = ct3_realize; pc->exit = ct3_exit; @@ -2477,9 +2483,11 @@ static void ct3_class_init(ObjectClass *oc, const void *data) set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); dc->desc = "CXL Memory Device (Type 3)"; - device_class_set_legacy_reset(dc, ct3d_reset); device_class_set_props(dc, ct3_props); + resettable_class_set_parent_phases(rc, NULL, ct3d_reset_hold, NULL, + &cvc->parent_phases); + cvc->get_lsa_size = get_lsa_size; cvc->get_lsa = get_lsa; cvc->set_lsa = set_lsa; diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h index ba551fa5f9..b7e20e3fe4 100644 --- a/include/hw/cxl/cxl_device.h +++ b/include/hw/cxl/cxl_device.h @@ -805,6 +805,8 @@ struct CXLType3Class { /* Private */ PCIDeviceClass parent_class; + ResettablePhases parent_phases; + /* public */ uint64_t (*get_lsa_size)(CXLType3Dev *ct3d); -- 2.43.0
