On Mon, Jun 22, 2026 at 11:39 PM Philippe Mathieu-Daudé <[email protected]> wrote: > > Hi Alistair, > > On 22/6/26 05:03, Alistair Francis wrote: > > On Sun, Jun 21, 2026 at 10:48 PM ZhengXiang Qin > > <[email protected]> wrote: > >> > >> check_zicbom_access() currently treats any probe_access_flags() result > >> other than TLB_INVALID_MASK as a successful access. However, a result > >> with TLB_MMIO means that the target is MMIO-like and should not be > >> treated as a normal cache block management target. > >> > >> Raise a store/AMO access fault for Zicbom accesses to MMIO-like regions > >> so that cbo.clean, cbo.flush and cbo.inval do not silently succeed on > >> non-cacheable/MMIO-like memory. > >> > >> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/3501 > >> Reviewed-by: Daniel Henrique Barboza <[email protected]> > >> Reviewed-by: Chao Liu <[email protected]> > >> Reviewed-by: Philippe Mathieu-Daudé <[email protected]> > >> Signed-off-by: ZhengXiang Qin <[email protected]> > > > > Thanks! > > > > Applied to riscv-to-apply.next > > > > Alistair > > > >> --- > >> Changes since v2: > >> - Add else before the success path for readability. > >> - Keep fault_addr as target_ulong since CPURISCVState::badaddr is > >> target_ulong. > > This is not true, the fields is uint64_t since this commit: > > commit f2287c7020f36e2f13622d9635a968d6f6fb507d > Author: Anton Johansson <[email protected]> > Date: Wed May 20 14:53:43 2026 +0200 > > target/riscv: Fix size of badaddr and bins > > Could you update the commit, or ask the contributor to repost, > or clean on top, please?
Thanks for catching this. I have dropped the patch, please rebase on master and send a new version Alistair
