On Mon, Jun 29, 2026 at 09:13:33AM +0800, Daniel Henrique Barboza wrote:
> We need to fault if reserved PTE bits (60:54) are set.
>
> Fixes: 0c54acb8243d ("hw/riscv: add RISC-V IOMMU base emulation")
> Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3554
> Signed-off-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Chao Liu <[email protected]>
> ---
> hw/riscv/riscv-iommu.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c
> index c9687e01a8..453601d7a5 100644
> --- a/hw/riscv/riscv-iommu.c
> +++ b/hw/riscv/riscv-iommu.c
> @@ -468,6 +468,8 @@ static int riscv_iommu_spa_fetch(RISCVIOMMUState *s,
> RISCVIOMMUContext *ctx,
>
> if (!(pte & PTE_V)) {
> break; /* Invalid PTE */
> + } else if (pte & PTE_RESERVED(false)) {
> + break; /* Reserved PTE bits set */
> } else if (!(pte & (PTE_R | PTE_W | PTE_X))) {
> base = PPN_PHYS(ppn); /* Inner PTE, continue walking */
> } else if ((pte & (PTE_R | PTE_W | PTE_X)) == PTE_W) {
> --
> 2.43.0
>
